| /XiangShan/ |
| H A D | .gitmodules | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| H A D | build.sc | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | ICacheMissUnit.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| H A D | ICache.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | WritebackQueue.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| H A D | MissQueue.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| /XiangShan/src/main/scala/xiangshan/ |
| H A D | XSTile.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| H A D | Parameters.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | DCacheWrapper.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|
| /XiangShan/src/main/scala/top/ |
| H A D | Configs.scala | diff 15ee59e46c33fe60e4408711f9ea0a6078d50510 Thu May 25 04:05:08 CEST 2023 wakafa <[email protected]> Merge coupledL2 into master (#2064)
* icache: Acquire -> Get to L2
* gitmodules: add coupledL2 as submodule
* cpl2: merge coupledL2 into master
* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2
* bump utility
* icache: remove unused releaseUnit
* config: minimalconfig includes l2
* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem
* bump Utility
* bump coupledL2: fix bugs in dual-core
* bump coupledL2
* icache: set icache as non-coherent node
* bump coupledL2: fix dirty problem in L2 ProbeAckData
---------
Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>
|