| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | StoreQueueData.scala | 42 val wdata = Input(Vec(numWrite, UInt(dataWidth.W))) // wdata: store addr constant
110 val wdata = Vec(numWrite, Input(UInt((XLEN/8).W))) constant
116 val wdata = Vec(numWrite, Input(Bool())) constant
287 val wdata = Vec(numWrite, Input(UInt(VLEN.W))) constant
293 val wdata = Vec(numWrite, Input(UInt((VLEN/8).W))) constant
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| H A D | LoadQueueData.scala | 48 val wdata = Input(Vec(numWrite, gen)) constant
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| H A D | StoreMisalignBuffer.scala | 576 val wdata = UInt(VLEN.W) constant
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| H A D | StoreQueue.scala | 1389 …val wdata = Mux(paddrModule.io.rdata(i)(3), dataModule.io.rdata(i).data(127, 64), dataModule.io.rd… constant
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| /XiangShan/src/main/scala/xiangshan/mem/ |
| H A D | MaskedDataModule.scala | 44 val wdata = Input(Vec(numWrite, gen)) constant
106 val wdata = Input(Vec(numWrite, gen)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ |
| H A D | PMPEntryModule.scala | 27 val wdata = io.in.wdata constant
95 val wdata = UInt(64.W) constant
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| H A D | PMAEntryModule.scala | 25 val wdata = io.in.wdata constant
103 val wdata = UInt(64.W) constant
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| H A D | CSRModule.scala | 91 val wdata = UInt(64.W) constant
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| H A D | CSRAIA.scala | 294 val wdata = ValidIO(new Bundle { constant
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| H A D | NewCSR.scala | 80 val wdata = UInt(64.W) constant
244 val wdata = io.in.bits.wdata constant
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| /XiangShan/src/main/scala/device/ |
| H A D | AXI4RAM.scala | 67 val wdata = VecInit.tabulate(beatBytes) { i => in.w.bits.data(8 * (i + 1) - 1, 8 * i) } constant
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| H A D | MemEncrypt.scala | 632 val wdata = Input(UInt(64.W)) constant
1001 val wdata = Wire(UInt(64.W)) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/data/ |
| H A D | DuplicatedDataArray.scala | 63 val wdata = Input(UInt(rowBits.W)) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/ |
| H A D | TagArray.scala | 70 val wdata = Mux(rst, rstVal, io.write.bits.asECCTag()) constant
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| H A D | LegacyMetaArray.scala | 68 val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt constant
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| /XiangShan/src/main/scala/xiangshan/mem/sbuffer/ |
| H A D | Sbuffer.scala | 945 val wdata = splitData & MaskExpand(splitMask) constant
962 val wdata = sbufferData & MaskExpand(sbufferMask) constant
1013 val wdata = (splitData & MaskExpand(splitMask)) << shiftBits constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | TLBStorage.scala | 42 val wdata = Input(gen) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | NewFtq.scala | 76 val wdata = Input(gen) constant
464 val wdata = Input(new Ftq_RF_Components) constant
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| /XiangShan/src/main/scala/xiangshan/backend/rob/ |
| H A D | Rob.scala | 1471 val wdata = Wire(Vec(CommitWidth, UInt(XLEN.W))) constant
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| /XiangShan/src/main/scala/xiangshan/ |
| H A D | Bundle.scala | 591 val wdata = Bool() // true.B by default constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | CSR.scala | 983 val wdata = MuxCase(wdata_tmp, Seq( constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | DCacheWrapper.scala | 1728 val wdata = IO(Input(UInt(64.W))) constant
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