Home
last modified time | relevance | path

Searched defs:valids (Results 1 – 13 of 13) sorted by relevance

/XiangShan/src/main/scala/utils/
H A DPipeWithFlush.scala34 val valids: Seq[Bool] = io.enq.valid +: Seq.fill(latency)(RegInit(false.B)) constant
H A DOverrideableQueue.scala12 val valids = Seq.fill(n){ RegInit(false.B) } constant
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/
H A DDatamoduleResultBuffer.scala51 val valids = RegInit(VecInit(Seq.fill(EnsbufferWidth)(false.B))) constant
H A DStorePrefetchBursts.scala94 val valids = RegInit(VecInit(List.tabulate(SIZE){_ => false.B})) constant
/XiangShan/src/main/scala/xiangshan/backend/rename/
H A DSnapshot.scala38 val valids = Output(Vec(RenameSnapshotNum, Bool())) constant
/XiangShan/src/main/scala/xiangshan/frontend/
H A DWrBypass.scala60 val valids = RegInit(0.U.asTypeOf(Vec(numEntries, Vec(numWays, Bool())))) constant
H A DITTAGE.scala157 val valids = VecInit((0 until RegionNums).map(w => regions(w).valid)) constant
401 val valids = RegInit(0.U.asTypeOf(Vec(nRows, Bool()))) constant
H A DTage.scala600 val valids = RegInit(VecInit(Seq.fill(nRowsPerBr)(false.B))) constant
/XiangShan/src/main/scala/xiangshan/mem/prefetch/
H A DL1StridePrefetcher.scala127 val valids = RegInit(VecInit(Seq.fill(STRIDE_ENTRY_NUM)(false.B))) constant
H A DFDP.scala84 val valids = RegInit(VecInit(Seq.fill(SIZE){ (false.B) })) constant
H A DSMSPrefetcher.scala159 val valids = entry_map(_ => RegInit(false.B)) constant
317 val valids = Seq.fill(smsParams.active_gen_table_size){ RegInit(false.B) } constant
932 val valids = Seq.fill(smsParams.pf_filter_size){ RegInit(false.B) } constant
1141 val valids = RegInit(VecInit(Seq.fill(smsParams.train_filter_size){ (false.B) })) constant
H A DL1StreamPrefetcher.scala179 val valids = RegInit(VecInit(Seq.fill(BIT_VEC_ARRAY_SIZE)(false.B))) constant
H A DL1PrefetchComponent.scala174 val valids = RegInit(VecInit(Seq.fill(size){ (false.B) })) constant