| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | AtomicsReplayUnit.scala | 36 val state = RegInit(s_invalid) constant
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| H A D | Probe.scala | 63 val state = RegInit(s_invalid) constant
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| H A D | WritebackQueue.scala | 149 val state = RegInit(s_invalid) constant
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| H A D | MissQueue.scala | 285 val state = RegInit(s_idle) constant
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| /XiangShan/src/main/scala/device/ |
| H A D | AXI4SlaveModule.scala | 94 val state = RegInit(s_idle) constant
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| /XiangShan/src/main/scala/xiangshan/mem/sbuffer/ |
| H A D | FakeSbuffer.scala | 49 val state = RegInit(s_invalid) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | Fence.scala | 49 val state = RegInit(s_idle) constant
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| H A D | Radix2Divider.scala | 39 val state = RegInit(s_idle) constant
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| H A D | SRT16Divider.scala | 63 val state = RegInit((1 << s_idle.litValue.toInt).U(7.W)) constant
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| H A D | SRT4Divider.scala | 57 val state = RegInit(UIntToOH(s_idle, 7)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/rob/ |
| H A D | RobDeqPtrWrapper.scala | 40 val state = Input(UInt(2.W)) constant
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| H A D | ExceptionGen.scala | 45 val state = ValidIO(new RobExceptionInfo) constant
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| H A D | Rab.scala | 110 val state = RegInit(s_idle) constant
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| H A D | Rob.scala | 290 val state = RegInit(s_idle) constant
307 val state = UInt(4.W) constant
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| /XiangShan/src/main/scala/xiangshan/mem/mdp/ |
| H A D | StoreSet.scala | 146 val state = RegInit(s_flush) constant
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| /XiangShan/src/main/scala/xiangshan/mem/pipeline/ |
| H A D | AtomicsUnit.scala | 69 val state = RegInit(s_invalid) constant
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | DecodeUnitComp.scala | 180 val state = RegInit(s_idle) constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | BitmapCheck.scala | 112 val state = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize+2)(state_idle))) constant
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| H A D | PageTableWalker.scala | 717 val state = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(state_idle))) constant
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VSegmentUnit.scala | 244 val state = RegInit(s_idle) constant
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| H A D | VecCommon.scala | 890 val state = RegInit(empty) constant
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| /XiangShan/src/main/scala/xiangshan/mem/ |
| H A D | MemBlock.scala | 1717 val state = RegInit(s_normal) constant
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