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Searched defs:s1_hit (Results 1 – 9 of 9) sorted by relevance

/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/
H A DStorePipe.scala134 val s1_hit = s1_has_permission && s1_new_hit_coh === s1_hit_coh && s1_tag_match.orR constant
/XiangShan/src/main/scala/xiangshan/cache/wpu/
H A DWPUWrapper.scala93 val s1_hit = Wire(Vec(nPorts, Bool())) constant
/XiangShan/src/main/scala/xiangshan/frontend/
H A DFauFTB.scala97 val s1_hit = s1_hit_oh.orR constant
H A DFTB.scala707 …val s1_hit = Mux(s1_close_ftb_req, false.B, ftbBank.io.read_hits.valid && io.ctrl.btb_enab… constant
/XiangShan/src/main/scala/xiangshan/mem/prefetch/
H A DL1StridePrefetcher.scala164 val s1_hit = RegEnable(s0_hit, s0_valid) constant
H A DL1StreamPrefetcher.scala273 val s1_hit = RegEnable(s0_hit, s0_valid) constant
H A DSMSPrefetcher.scala176 val s1_hit = GatedValidRegNext(s0_hit) && io.s1_valid constant
951 val s1_hit = Wire(Bool()) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/
H A DLoadPipe.scala303 val s1_hit = s1_tag_match_dup_dc && s1_has_permission && s1_hit_coh === s1_new_hit_coh constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/
H A DMainPipe.scala393 val s1_hit = s1_tag_match && s1_has_permission constant