| /XiangShan/src/main/scala/device/TLPMA/ |
| H A D | TLPMA.scala | 16 val resp = Vec(mmpma.num, new PMPRespBundle()) constant
31 val resp = io.resp constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/ |
| H A D | TagArray.scala | 60 val resp = Output(Vec(DCacheWayDiv, UInt(encTagBits.W))) constant
103 val resp = Output(Vec(nWays, UInt(encTagBits.W))) constant
123 val resp = Output(Vec(readPorts, Vec(nWays, UInt(encTagBits.W)))) constant
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| H A D | AsynchronousMetaArray.scala | 54 val resp = Output(Vec(readPorts, Vec(nWays, new Meta))) constant
113 val resp = Output(Vec(readPorts, Vec(nWays, Bool()))) constant
174 val resp = Output(Vec(readPorts, Vec(nWays, UInt(L1PfSourceBits.W)))) constant
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| H A D | LegacyMetaArray.scala | 62 val resp = Output(Vec(nWays, UInt(encMetaBits.W))) constant
135 val resp = Output(Vec(numReadPorts, Vec(nWays, UInt(encMetaBits.W)))) constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | PageTableWalker.scala | 58 val resp = DecoupledIO(new Bundle { constant
61 val resp = new PtwMergeResp constant
75 val resp = Flipped(Valid(new Bundle { constant
81 val resp = Flipped(ValidIO(UInt(XLEN.W))) constant
86 val resp = Flipped(new PMPRespBundle()) constant
95 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) constant
657 val resp = Flipped(Valid(new Bundle { constant
670 val resp = Flipped(new PMPRespBundle()) constant
678 val resp = Flipped(Valid(new Bundle { constant
685 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) constant
[all …]
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| H A D | BitmapCheck.scala | 62 val resp = Flipped(DecoupledIO(new Bundle { constant
69 val resp = DecoupledIO(new bitmapRespBundle()) constant
73 val resp = Flipped(new PMPRespBundle()) constant
88 val resp = Flipped(DecoupledIO(new bitmapCacheRespBundle())) constant
339 val resp = DecoupledIO(new bitmapCacheRespBundle()) constant
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| H A D | TLBStorage.scala | 106 val resp = io.r.resp(i) constant
285 val resp = io.r.resp(i) constant
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| H A D | MMUBundle.scala | 158 val resp = Output(Vec(readWidth, Vec(set, Bool()))) constant
419 val resp = Vec(ports, ValidIO(new Bundle{ constant
460 val resp = Vec(ports, ValidIO(new Bundle{ constant
589 val resp = Flipped(DecoupledIO(new TlbResp(nRespDups))) constant
594 val resp = Flipped(DecoupledIO(new PtwRespS2)) constant
604 val resp = Flipped(DecoupledIO(new PtwRespS2withMemIdx())) constant
629 val resp = ValidIO(new TLBHintResp) constant
671 val resp = Flipped(DecoupledIO(new Bundle { constant
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| H A D | Repeater.scala | 60 val resp = RegEnable(ptw.resp.bits, ptw.resp.fire) constant
114 val resp = RegEnable(ptw.resp.bits, ptw.resp.fire) constant
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| /XiangShan/src/main/scala/utils/ |
| H A D | AXI4Lite.scala | 39 val resp = UInt(2.W) constant
44 val resp = UInt(2.W) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | InstrUncache.scala | 49 val resp: DecoupledIO[InsUncacheResp] = DecoupledIO(new InsUncacheResp) constant
148 val resp: DecoupledIO[InsUncacheResp] = DecoupledIO(new InsUncacheResp) constant
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| H A D | ICacheMainPipe.scala | 53 val resp: Valid[ICacheMainPipeResp] = ValidIO(new ICacheMainPipeResp) constant
70 val resp: Valid[ICacheMissResp] = Flipped(ValidIO(new ICacheMissResp)) constant
75 val resp: PMPRespBundle = Input(new PMPRespBundle()) constant
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| H A D | ICacheMissUnit.scala | 107 val resp: Valid[MSHRResp] = ValidIO(new MSHRResp) constant
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| /XiangShan/src/main/scala/xiangshan/cache/wpu/ |
| H A D | WPUWrapper.scala | 63 val resp = Vec(nPorts, ValidIO(new WPUResp(nWays))) constant
73 val resp = Vec(nPorts, ValidIO(new WPUResp(nWays))) constant
240 val resp = Output(new Bundle{ constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | PMP.scala | 406 val resp = Wire(new PMPRespBundle) constant
485 val resp = new PMPRespBundle() constant
514 val resp = Output(new PMPConfig()) constant
576 val resp = Wire(new PMPRespBundle) constant
592 val resp = if (pmpUsed) (resp_pmp | resp_pma | resp_keyid) else (resp_pma | resp_keyid) constant
619 val resp = and(res_pmp, res_pma) constant
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| H A D | PMA.scala | 212 val resp = Wire(new PMPRespBundle) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/data/ |
| H A D | AbstractDataArray.scala | 47 val resp = Output(Vec(3, Vec(blockRows, Bits(encRowBits.W)))) constant
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| /XiangShan/src/main/scala/xiangshan/mem/prefetch/ |
| H A D | FDP.scala | 52 val resp = Input(Bool()) constant
175 val resp = Vec(LoadPipelineWidth, ValidIO(new BloomRespBundle)) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/ |
| H A D | StorePipe.scala | 43 val resp = Flipped(DecoupledIO(new DCacheBundle() { constant
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| /XiangShan/src/main/scala/xiangshan/backend/rename/ |
| H A D | BusyTable.scala | 32 val resp = Output(Bool()) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | FauFTB.scala | 46 val resp = Output(new FauFTBEntry) constant
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| /XiangShan/src/main/scala/device/ |
| H A D | MemEncryptUtil.scala | 240 val resp = UInt(params.respBits.W) constant
379 val resp = DecoupledIO(new Bundle { constant
571 val resp = DecoupledIO(new Bundle { constant
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VecBundle.scala | 192 val resp = Flipped(ValidIO(new MergeBufferResp(isVStore))) constant
197 val resp = ValidIO(new MergeBufferResp(isVStore)) constant
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| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | LoadMisalignBuffer.scala | 510 val resp = io.splitLoadResp.bits constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/ |
| H A D | LoadPipe.scala | 106 val resp = Flipped(ValidIO(new BloomRespBundle())) constant
437 val resp = Wire(ValidIO(new DCacheWordResp)) constant
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