1package xiangshan.backend.fu.vector.utils 2 3import chisel3._ 4 5class VecDataSplitIO(inDataWidth: Int, outDataWidth: Int) extends Bundle { 6 val inVecData = Input(UInt(inDataWidth.W)) 7 val outVec8b = Output(Vec(inDataWidth / 8, UInt( 8.W))) 8 val outVec16b = Output(Vec(inDataWidth / 16, UInt(16.W))) 9 val outVec32b = Output(Vec(inDataWidth / 32, UInt(32.W))) 10 val outVec64b = Output(Vec(inDataWidth / 64, UInt(64.W))) 11} 12 13class VecDataSplitModule(inDataWidth: Int, outDataWidth: Int) extends Module { 14 val io = IO(new VecDataSplitIO(inDataWidth, outDataWidth)) 15 16 private val inData = io.inVecData 17 private val vec8b = Wire(Vec(inDataWidth / 8, UInt( 8.W))) 18 private val vec16b = Wire(Vec(inDataWidth / 16, UInt(16.W))) 19 private val vec32b = Wire(Vec(inDataWidth / 32, UInt(32.W))) 20 private val vec64b = Wire(Vec(inDataWidth / 64, UInt(64.W))) 21 22 vec8b := inData.asTypeOf(vec8b) 23 vec16b := inData.asTypeOf(vec16b) 24 vec32b := inData.asTypeOf(vec32b) 25 vec64b := inData.asTypeOf(vec64b) 26 27 io.outVec64b.zip(vec64b).foreach { case(sink, source) => sink := source } 28 io.outVec32b.zip(vec32b).foreach { case(sink, source) => sink := source } 29 io.outVec16b.zip(vec16b).foreach { case(sink, source) => sink := source } 30 io.outVec8b .zip(vec8b) .foreach { case(sink, source) => sink := source } 31} 32