Searched defs:mem (Results 1 – 9 of 9) sorted by relevance
| /XiangShan/src/main/scala/device/ |
| H A D | AXI4RAM.scala | 54 val mem = DifftestMem(memByte, beatBytes) constant
65 val mem = Mem(memByte / beatBytes, Vec(beatBytes, UInt(8.W))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | BypassNetwork.scala | 32 val mem: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = Flipped(memSchdParams.genExuInputBundle) constant
45 val mem: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputCopySrcBundle constant
52 …val mem: MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = Flipped(memSchdParams.genExuBypassValidBun… constant
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| /XiangShan/src/main/scala/xiangshan/backend/regcache/ |
| H A D | RegCacheDataModule.scala | 58 val mem = Reg(Vec(numEntries, UInt(dataWidth.W))) constant
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| /XiangShan/scripts/ |
| H A D | vlsi_mem_gen | 85 def generate(self, mem): argument
124 def generate(self, mem): argument
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | PageTableWalker.scala | 79 val mem = new Bundle { constant
102 val mem = io.mem constant
655 val mem = new Bundle { constant
1133 val mem = new Bundle { constant
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| H A D | BitmapCheck.scala | 60 val mem = new Bundle { constant
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| /XiangShan/src/main/scala/xiangshan/backend/regfile/ |
| H A D | Regfile.scala | 85 val mem = Reg(Vec(numPregs, UInt(len.W))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/ |
| H A D | Backend.scala | 1079 val mem = new BackendMemIO constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | NewFtq.scala | 468 …val mem = Module(new SyncDataModuleTemplate(new Ftq_RF_Components, FtqSize, num_pc_read, 1… constant
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