| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | WrBypass.scala | 44 val hit = Output(Bool()) constant
66 val hit = hits_oh.reduce(_ || _) constant
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| H A D | FauFTB.scala | 80 val hit = Bool() constant
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| H A D | FTB.scala | 427 val hit = Bool() constant
538 val hit = total_hits.reduce(_ || _) constant
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| H A D | NewFtq.scala | 258 val hit = Input(Bool()) constant
277 val hit = io.hit constant
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| H A D | BPU.scala | 589 val hit = Vec(numDup, Bool()) constant
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| H A D | FrontendBundle.scala | 558 val hit = Bool() constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | BitmapCheck.scala | 51 val hit = Bool() constant
206 val hit = WireInit(false.B) constant
328 val hit = Bool() constant
349 def hit(tag : UInt) = { method
393 val hit = ParallelOR(hitVec) constant
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| H A D | PageTableCache.scala | 40 val hit = Bool() constant
76 val hit = Bool() constant
134 val hit = Bool() constant
419 val hit = DataHoldBypass(ParallelOR(hitVec), stageDelay_valid_1cycle) constant
453 val hit = DataHoldBypass(ParallelOR(hitVec), stageDelay_valid_1cycle) constant
504 val hit = ParallelOR(hitVec) constant
572 val hit = WireInit(false.B) constant
631 val hit = WireInit(false.B) constant
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| H A D | MMUBundle.scala | 217 …def hit(vpn: UInt, asid: UInt, nSets: Int = 1, ignoreAsid: Boolean = false, vmid: UInt, hasS2xlate… method
420 val hit = Output(Bool()) constant
461 val hit = Output(Bool()) constant
858 …def hit(vpn: UInt, asid: UInt, vasid: UInt, vmid: UInt, allType: Boolean = false, ignoreAsid: Bool… method
981 …def hit(vpn: UInt, asid: UInt, vasid: UInt, vmid:UInt, ignoreAsid: Boolean = false, s2xlate: Bool)… method
1142 def hit(gvpn: UInt, vmid: UInt): Bool = { method
1193 …def hit(vpn: UInt, asid: UInt, vmid: UInt, allType: Boolean = false, ignoreAsid: Boolean = false, … method
1305 …def hit(vpn: UInt, asid: UInt, vasid: UInt, vmid: UInt, allType: Boolean = false, ignoreAsid: Bool… method
1392 val hit = Bool() constant
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| H A D | TLBStorage.scala | 118 …val hit = e._1.hit(vpn, Mux(hasS2xlate, io.csr.vsatp.asid, io.csr.satp.asid), vmid = io.csr.hgatp.… constant
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| H A D | TLB.scala | 304 val hit = e_hit || p_hit constant
557 …val hit = Mux(onlyS2, hit_s2, hit_s1) && io.ptw.resp.valid && miss_req_s2xlate_reg === io.ptw.resp… constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | ICacheMainPipe.scala | 89 val hit: Bool = Bool() constant
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| H A D | ICacheMissUnit.scala | 86 val hit: Bool = Input(Bool()) constant
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VecBundle.scala | 97 val hit = Bool() constant
109 val hit = Bool() constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | MissQueue.scala | 87 def hit = req_coh.isValid() method
403 def hit(e_vaddr: UInt): Bool = { method
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| /XiangShan/src/main/scala/xiangshan/backend/fu/util/ |
| H A D | Trigger.scala | 91 val hit = Bool() // [20] constant
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| /XiangShan/src/main/scala/xiangshan/ |
| H A D | Bundle.scala | 91 val hit = if (!env.FPGAPlatform) Bool() else UInt(0.W) constant
447 val hit = Bool() constant
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