1 #ifndef _PPC4xx_UIC_H_ 2 #define _PPC4xx_UIC_H_ 3 4 /* 5 * Define the number of UIC's 6 */ 7 #define UIC_MAX 1 8 #define IRQ_MAX UIC_MAX * 32 9 10 /* UIC0 dcr base address */ 11 #define UIC0_DCR_BASE 0xc0 12 13 /* 14 * UIC register 15 */ 16 #define UIC_SR 0x0 /* UIC status */ 17 #define UIC_ER 0x2 /* UIC enable */ 18 #define UIC_CR 0x3 /* UIC critical */ 19 #define UIC_PR 0x4 /* UIC polarity */ 20 #define UIC_TR 0x5 /* UIC triggering */ 21 #define UIC_MSR 0x6 /* UIC masked status */ 22 #define UIC_VR 0x7 /* UIC vector */ 23 #define UIC_VCR 0x8 /* UIC vector configuration */ 24 25 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ 26 #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ 27 #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ 28 #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ 29 #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ 30 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ 31 #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ 32 #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ 33 34 /* The following is for compatibility with 405 code */ 35 #define uicsr uic0sr 36 #define uicer uic0er 37 #define uiccr uic0cr 38 #define uicpr uic0pr 39 #define uictr uic0tr 40 #define uicmsr uic0msr 41 #define uicvr uic0vr 42 #define uicvcr uic0vcr 43 44 /* the interrupt vector definitions */ 45 #define VECNUM_MAL_SERR 10 46 #define VECNUM_MAL_TXEOB 11 47 #define VECNUM_MAL_RXEOB 12 48 #define VECNUM_MAL_TXDE 13 49 #define VECNUM_MAL_RXDE 14 50 #define VECNUM_ETH0 15 51 #define VECNUM_ETH1_OFFS 2 52 #define VECNUM_EIRQ6 29 53 54 /* 55 * Mask definitions (used for example in 4xx_enet.c) 56 */ 57 #define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) 58 /* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ 59 #define UIC_NR(vec) ((vec) >> 5) 60 61 #endif /* _PPC4xx_UIC_H_ */ 62