1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/interrupt_props.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <plat/common/common_def.h> 15 #include "socfpga_plat_def.h" 16 17 /* Platform Type */ 18 #define PLAT_SOCFPGA_STRATIX10 1 19 #define PLAT_SOCFPGA_AGILEX 2 20 #define PLAT_SOCFPGA_N5X 3 21 #define PLAT_SOCFPGA_AGILEX5 4 22 #define SIMICS_RUN 1 23 #define MAX_IO_MTD_DEVICES U(1) 24 25 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 26 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 27 28 /* Magic word to indicate L2 reset is completed */ 29 #define L2_RESET_DONE_STATUS 0x1228E5E7 30 31 /* Define next boot image name and offset */ 32 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 33 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 34 35 #ifndef PRELOADED_BL33_BASE 36 #define PLAT_NS_IMAGE_OFFSET 0x80200000 37 #else 38 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 39 #endif 40 #define PLAT_HANDOFF_OFFSET 0x0003F000 41 42 #else 43 #define PLAT_NS_IMAGE_OFFSET 0x10000000 44 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 45 #endif 46 47 #define PLAT_QSPI_DATA_BASE (0x3C00000) 48 #define PLAT_NAND_DATA_BASE (0x0200000) 49 #define PLAT_SDMMC_DATA_BASE (0x0) 50 51 /******************************************************************************* 52 * Platform binary types for linking 53 ******************************************************************************/ 54 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 55 #define PLATFORM_LINKER_ARCH aarch64 56 57 /* SoCFPGA supports up to 124GB RAM */ 58 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 59 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 60 61 62 /******************************************************************************* 63 * Generic platform constants 64 ******************************************************************************/ 65 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 66 67 /* Size of cacheable stacks */ 68 #define PLATFORM_STACK_SIZE 0x2000 69 70 /* PSCI related constant */ 71 #define PLAT_NUM_POWER_DOMAINS 5 72 #define PLAT_MAX_PWR_LVL 1 73 #define PLAT_MAX_RET_STATE 1 74 #define PLAT_MAX_OFF_STATE 2 75 #define PLATFORM_SYSTEM_COUNT U(1) 76 #define PLATFORM_CLUSTER_COUNT U(1) 77 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 78 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 79 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 80 PLATFORM_CLUSTER0_CORE_COUNT) 81 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 82 83 /* Interrupt related constant */ 84 85 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 86 87 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 88 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 89 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 90 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 91 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 92 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 93 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 94 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 95 96 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 97 #define TSP_SEC_MEM_BASE BL32_BASE 98 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 99 100 101 /******************************************************************************* 102 * BL31 specific defines. 103 ******************************************************************************/ 104 /* 105 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 106 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 107 * little space for growth. 108 */ 109 110 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 111 112 #define BL1_RO_BASE (0xffe00000) 113 #define BL1_RO_LIMIT (0xffe0f000) 114 #define BL1_RW_BASE (0xffe10000) 115 #define BL1_RW_LIMIT (0xffe1ffff) 116 #define BL1_RW_SIZE (0x14000) 117 118 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 119 120 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 121 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 122 123 #define CMP_ENTRY 0xFFE3EFF8 124 125 #define PLAT_SEC_WARM_ENTRY 0 126 127 /******************************************************************************* 128 * Platform specific page table and MMU setup constants 129 ******************************************************************************/ 130 #define MAX_XLAT_TABLES 8 131 #define MAX_MMAP_REGIONS 16 132 133 /******************************************************************************* 134 * Declarations and constants to access the mailboxes safely. Each mailbox is 135 * aligned on the biggest cache line size in the platform. This is known only 136 * to the platform as it might have a combination of integrated and external 137 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 138 * line at any cache level. They could belong to different cpus/clusters & 139 * get written while being protected by different locks causing corruption of 140 * a valid mailbox address. 141 ******************************************************************************/ 142 #define CACHE_WRITEBACK_SHIFT 6 143 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 144 145 /******************************************************************************* 146 * UART related constants 147 ******************************************************************************/ 148 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 149 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 150 151 #define PLAT_BAUDRATE (115200) 152 #define PLAT_UART_CLOCK (100000000) 153 154 /******************************************************************************* 155 * PHY related constants 156 ******************************************************************************/ 157 158 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 159 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 160 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 161 162 /******************************************************************************* 163 * GIC related constants 164 ******************************************************************************/ 165 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 166 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 167 168 /******************************************************************************* 169 * System counter frequency related constants 170 ******************************************************************************/ 171 172 /* 173 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 174 * terminology. On a GICv2 system or mode, the lists will be merged and treated 175 * as Group 0 interrupts. 176 */ 177 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 178 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 179 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 180 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 181 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 182 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 183 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 184 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 185 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 186 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 187 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 188 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 189 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 190 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 191 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 192 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 193 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 194 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 195 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 196 197 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 198 199 #define MAX_IO_HANDLES 4 200 #define MAX_IO_DEVICES 4 201 #define MAX_IO_BLOCK_DEVICES 2 202 203 #ifndef __ASSEMBLER__ 204 struct socfpga_bl31_params { 205 param_header_t h; 206 image_info_t *bl31_image_info; 207 entry_point_info_t *bl32_ep_info; 208 image_info_t *bl32_image_info; 209 entry_point_info_t *bl33_ep_info; 210 image_info_t *bl33_image_info; 211 }; 212 #endif 213 214 #endif /* PLATFORM_DEF_H */ 215