Lines Matching full:enable
21 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
22 #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
23 #define MSR_SPE (1<<25) /* Enable SPE(e500) */
24 #define MSR_POW (1<<18) /* Enable Power Management */
25 #define MSR_WE (1<<18) /* Wait State Enable */
27 #define MSR_CE (1<<17) /* Critical Interrupt Enable */
29 #define MSR_EE (1<<15) /* External Interrupt Enable */
31 #define MSR_FP (1<<13) /* Floating Point enable */
32 #define MSR_ME (1<<12) /* Machine Check Enable */
35 #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
36 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
38 #define MSR_DE (1<<9) /* Debug Exception Enable */
45 #define MSR_PE (1<<3) /* Protection Enable */
85 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
86 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
87 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
88 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
89 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
145 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
146 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
147 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
148 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
154 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
155 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
160 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
161 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
162 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
163 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
237 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
238 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
239 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
248 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
249 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
250 #define HID0_TBEN (1<<14) /* Time Base Enable */
257 #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
258 #define HID0_SGE (1<<7) /* Store Gathering Enable */
261 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
262 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
263 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
266 #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
268 #define HID1_ABE (1<<12) /* Address broadcast enable */
393 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
394 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
400 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
401 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
418 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
478 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
480 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
482 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
484 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
487 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
488 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
753 #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
754 #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
755 #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
756 #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
757 #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
758 #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
759 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
760 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
761 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
762 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
763 #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
764 #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
765 #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
766 #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
767 #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */