Lines Matching +full:host +full:- +full:side
1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 /* Define bits and masks for real-mode storage attribute control registers */
68 /* values for kiar register - indirect addressing of these regs */
102 /* values for ebccfga register - indirect addressing of these regs */
233 #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
340 *-------------------------------------------------------------------------------
343 *-------------------------------------------------------------------------------
560 /* 0x08-0x0F Reserved */
565 /* 0x14-0x1F Reserved */
687 /*-----------------------------------------------------------------------------
689 '----------------------------------------------------------------------------*/
706 /*-----------------------------------------------------------------------------
708 '----------------------------------------------------------------------------*/
733 #define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
734 #define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
735 #define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
736 #define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
737 #define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
738 #define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
739 #define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
742 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
743 #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
744 #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
745 #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */