Lines Matching full:7
51 #define CP0_INFO $7
111 #define CP0_TX39_CACHE $7
240 /* bits 6 & 7 are reserved on R[23]000 */
324 #define STATUSB_IP15 7
325 #define STATUSF_IP15 (_ULCAST_(1) << 7)
382 #define CONF_CM_CACHABLE_ACCELERATED 7
383 #define CONF_CM_CMASK 7
390 #define CONF_DC (_ULCAST_(7) << 6)
391 #define CONF_IC (_ULCAST_(7) << 9)
398 #define CONF_EC (_ULCAST_(7) << 28)
422 #define R10K_CONF_PM (_ULCAST_(3) << 7)
426 #define R10K_CONF_SS (_ULCAST_(7) << 16)
427 #define R10K_CONF_SC (_ULCAST_(7) << 19)
428 #define R10K_CONF_DC (_ULCAST_(7) << 26)
429 #define R10K_CONF_IC (_ULCAST_(7) << 29)
442 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
454 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
455 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
469 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
470 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
471 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
472 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
473 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
474 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
484 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
492 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
524 #define CE0_QW_WB_SECONDARY 7
544 #define CE1_TLB_REFILL 7
624 #define read_c0_info() __read_32bit_c0_register($7, 0)
626 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
627 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
638 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
639 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
650 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
651 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)