Lines Matching full:7
22 * 2016��9��7�� Urey the first version
97 #define REG_A3 7 /* arg reg 3 …
105 #define REG_T7 15 /* caller saved 7 …
113 #define REG_S7 23 /* callee saved 7 …
154 #define FP32CTX_14 (FP32CTX_0 + (7 * 8))
172 #define FP64CTX_14 (FP64CTX_0 + (7 * 8))
187 #define FP64CTX_13 (FP64CTX_30 + (7 * 8))
232 #define CP0_INFO $7
282 #define CP0_TX39_CACHE $7
431 /* bits 6 & 7 are reserved on R[23]000 */
510 #define STATUSB_IP15 7
511 #define STATUSF_IP15 (_ULCAST_(1) << 7)
569 #define CONF_CM_CACHABLE_ACCELERATED 7
570 #define CONF_CM_CMASK 7
577 #define CONF_DC (_ULCAST_(7) << 6)
578 #define CONF_IC (_ULCAST_(7) << 9)
585 #define CONF_EC (_ULCAST_(7) << 28)
601 #define R10K_CONF_PM (_ULCAST_(3) << 7)
605 #define R10K_CONF_SS (_ULCAST_(7) << 16)
606 #define R10K_CONF_SC (_ULCAST_(7) << 19)
607 #define R10K_CONF_DC (_ULCAST_(7) << 26)
608 #define R10K_CONF_IC (_ULCAST_(7) << 29)
621 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
633 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
634 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
656 #define CE0_QW_WB_SECONDARY 7
676 #define CE1_TLB_REFILL 7
887 #define read_c0_info() __read_32bit_c0_register($7, 0)
889 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
890 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
928 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
936 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
948 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
957 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)