Lines Matching full:delay
508 ;// <i> The delay is in EMCCLK cycles
513 ;// <i> The delay is in EMCCLK cycles
518 ;// <i> The delay is in CCLK cycles
524 ;// <i> The delay is in CCLK cycles
529 ;// <i> The delay is in CCLK cycles
534 ;// <i> The delay is in CCLK cycles
539 ;// <i> The delay is in CCLK cycles
544 ;// <i> The delay is in CCLK cycles
549 ;// <i> The delay is in CCLK cycles
554 ;// <i> The delay is in CCLK cycles
559 ;// <i> The delay is in CCLK cycles
606 ;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0)
612 ;// <o0.0..1> RAS: RAS latency (active to read/write delay)
653 ;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1)
659 ;// <o0.0..1> RAS: RAS latency (active to read/write delay)
699 ;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS2)
705 ;// <o0.0..1> RAS: RAS latency (active to read/write delay)
745 ;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS3)
751 ;// <o0.0..1> RAS: RAS latency (active to read/write delay)
789 ;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0)
790 ;// <i> Selects the delay from CS0 to write enable
792 ;// <i> The delay is in CCLK cycles
796 ;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen0)
797 ;// <i> Selects the delay from CS0 or address change, whichever is later, to output enable
799 ;// <i> The delay is in CCLK cycles
803 ;// <h> Static Memory Read Delay Register (EMCStaticWaitRd0)
804 ;// <i> Selects the delay from CS0 to a read access
806 ;// <i> The delay is in CCLK cycles
810 ;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
811 ;// <i> Selects the delay for asynchronous page mode sequential accesses for CS0
813 ;// <i> The delay is in CCLK cycles
817 ;// <h> Static Memory Write Delay Register (EMCStaticWaitWr0)
818 ;// <i> Selects the delay from CS0 to a write access
820 ;// <i> The delay is in CCLK cycles
824 ;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0)
827 ;// <i> The delay is in CCLK cycles
856 ;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1)
857 ;// <i> Selects the delay from CS1 to write enable
859 ;// <i> The delay is in CCLK cycles
863 ;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen1)
864 ;// <i> Selects the delay from CS1 or address change, whichever is later, to output enable
866 ;// <i> The delay is in CCLK cycles
870 ;// <h> Static Memory Read Delay Register (EMCStaticWaitRd1)
871 ;// <i> Selects the delay from CS1 to a read access
873 ;// <i> The delay is in CCLK cycles
877 ;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
878 ;// <i> Selects the delay for asynchronous page mode sequential accesses for CS1
880 ;// <i> The delay is in CCLK cycles
884 ;// <h> Static Memory Write Delay Register (EMCStaticWaitWr1)
885 ;// <i> Selects the delay from CS1 to a write access
887 ;// <i> The delay is in CCLK cycles
891 ;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1)
894 ;// <i> The delay is in CCLK cycles
923 ;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen2)
924 ;// <i> Selects the delay from CS2 to write enable
926 ;// <i> The delay is in CCLK cycles
930 ;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen2)
931 ;// <i> Selects the delay from CS2 or address change, whichever is later, to output enable
933 ;// <i> The delay is in CCLK cycles
937 ;// <h> Static Memory Read Delay Register (EMCStaticWaitRd2)
938 ;// <i> Selects the delay from CS2 to a read access
940 ;// <i> The delay is in CCLK cycles
944 ;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2)
945 ;// <i> Selects the delay for asynchronous page mode sequential accesses for CS2
947 ;// <i> The delay is in CCLK cycles
951 ;// <h> Static Memory Write Delay Register (EMCStaticWaitWr2)
952 ;// <i> Selects the delay from CS2 to a write access
954 ;// <i> The delay is in CCLK cycles
958 ;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn2)
961 ;// <i> The delay is in CCLK cycles
990 ;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen3)
991 ;// <i> Selects the delay from CS3 to write enable
993 ;// <i> The delay is in CCLK cycles
997 ;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen3)
998 ;// <i> Selects the delay from CS3 or address change, whichever is later, to output enable
1000 ;// <i> The delay is in CCLK cycles
1004 ;// <h> Static Memory Read Delay Register (EMCStaticWaitRd3)
1005 ;// <i> Selects the delay from CS3 to a read access
1007 ;// <i> The delay is in CCLK cycles
1011 ;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3)
1012 ;// <i> Selects the delay for asynchronous page mode sequential accesses for CS3
1014 ;// <i> The delay is in CCLK cycles
1018 ;// <h> Static Memory Write Delay Register (EMCStaticWaitWr3)
1019 ;// <i> Selects the delay from CS3 to a write access
1021 ;// <i> The delay is in CCLK cycles
1025 ;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn3)
1028 ;// <i> The delay is in CCLK cycles
1037 ;// <i> The delay is in (16 * CCLK) cycles
1315 LDR R6, =1440000 ; Number of cycles to delay
1316 Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz
1322 LDR R6, =2880000 ; Number of cycles to delay
1323 Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz
1332 MOV R6, #64 ; Number of cycles to delay
1333 Wait_2 SUBS R6, R6, #1 ; Delay
1389 LDR R6, =14400 ; Number of cycles to delay
1390 Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz
1398 LDR R6, =1440000 ; Number of cycles to delay
1399 Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz
1470 LDR R6, =144000 ; Number of cycles to delay
1471 Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz