15 	register rt_uint32_t value;  in mmu_setttbase()  local
19 	 * in that case access controlled by permission value  in mmu_setttbase()
22 	value = 0;  in mmu_setttbase()
25 		mcr p15, 0, value, c8, c7, 0  in mmu_setttbase()
28 	value = 0x55555555;  in mmu_setttbase()
31 		mcr p15, 0, value, c3, c0, 0  in mmu_setttbase()
46 	register rt_uint32_t value;  in mmu_enable()  local
50 		mrc p15, 0, value, c1, c0, 0  in mmu_enable()
51 			orr value, value, #0x01  in mmu_enable()
52 			mcr p15, 0, value, c1, c0, 0  in mmu_enable()
58 	register rt_uint32_t value;  in mmu_disable()  local
62 		mrc p15, 0, value, c1, c0, 0  in mmu_disable()
63 			bic value, value, #0x01  in mmu_disable()
64 			mcr p15, 0, value, c1, c0, 0  in mmu_disable()
70 	register rt_uint32_t value;  in mmu_enable_icache()  local
74 		mrc p15, 0, value, c1, c0, 0  in mmu_enable_icache()
75 			orr value, value, #0x1000  in mmu_enable_icache()
76 			mcr p15, 0, value, c1, c0, 0  in mmu_enable_icache()
82 	register rt_uint32_t value;  in mmu_enable_dcache()  local
86 		mrc p15, 0, value, c1, c0, 0  in mmu_enable_dcache()
87 			orr value, value, #0x04  in mmu_enable_dcache()
88 			mcr p15, 0, value, c1, c0, 0  in mmu_enable_dcache()
94 	register rt_uint32_t value;  in mmu_disable_icache()  local
98 		mrc p15, 0, value, c1, c0, 0  in mmu_disable_icache()
99 			bic value, value, #0x1000  in mmu_disable_icache()
100 			mcr p15, 0, value, c1, c0, 0  in mmu_disable_icache()
106 	register rt_uint32_t value;  in mmu_disable_dcache()  local
110 		mrc p15, 0, value, c1, c0, 0  in mmu_disable_dcache()
111 			bic value, value, #0x04  in mmu_disable_dcache()
112 			mcr p15, 0, value, c1, c0, 0  in mmu_disable_dcache()
118 	register rt_uint32_t value;  in mmu_enable_alignfault()  local
122 		mrc p15, 0, value, c1, c0, 0  in mmu_enable_alignfault()
123 			orr value, value, #0x02  in mmu_enable_alignfault()
124 			mcr p15, 0, value, c1, c0, 0  in mmu_enable_alignfault()
130 	register rt_uint32_t value;  in mmu_disable_alignfault()  local
134 		mrc p15, 0, value, c1, c0, 0  in mmu_disable_alignfault()
135 			bic value, value, #0x02  in mmu_disable_alignfault()
136 			mcr p15, 0, value, c1, c0, 0  in mmu_disable_alignfault()
198 	register rt_uint32_t value;  in mmu_invalidate_tlb()  local
200 	value = 0;  in mmu_invalidate_tlb()
203 		mcr p15, 0, value, c8, c7, 0  in mmu_invalidate_tlb()
209 	register rt_uint32_t value;  in mmu_invalidate_icache()  local
211 	value = 0;  in mmu_invalidate_icache()
215 		mcr p15, 0, value, c7, c5, 0  in mmu_invalidate_icache()
222 	register rt_uint32_t value;  in mmu_invalidate_dcache_all()  local
224 	value = 0;  in mmu_invalidate_dcache_all()
228 		mcr p15, 0, value, c7, c6, 0  in mmu_invalidate_dcache_all()
234 	register rt_uint32_t value;  in mmu_setttbase()  local
238 	 * in that case access controlled by permission value  in mmu_setttbase()
241 	value = 0;  in mmu_setttbase()
242 	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));  in mmu_setttbase()
244 	value = 0x55555555;  in mmu_setttbase()
245 	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));  in mmu_setttbase()