Lines Matching full:read

190 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
191 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
197 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
198 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
207 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
208 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
214 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
215 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
221 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
224 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
225 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
227 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
230 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
231 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
326 /* Description: Status to indicate if data sent from the debugger to the CPU has been read */
342 /* Description: Status to indicate if data sent from the CPU to the debugger status has been read */
517 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
518 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
524 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
525 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
531 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
532 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
538 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
539 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
545 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
546 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
552 #define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
553 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
559 #define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
560 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
566 #define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
567 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
573 #define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
574 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
580 #define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
581 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
587 #define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
588 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
594 #define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
595 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
601 #define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
602 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
608 #define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
609 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
615 #define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
616 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
622 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
623 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
632 #define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
633 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
639 #define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
640 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
646 #define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
647 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
653 #define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
654 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
660 #define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
661 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
667 #define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
668 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
674 #define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
675 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
681 #define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
682 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
688 #define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
689 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
695 #define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
696 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
702 #define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
703 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
709 #define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
710 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
716 #define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
717 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
723 #define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
724 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
730 #define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
731 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
737 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
738 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
992 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
993 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
999 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1000 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1006 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1007 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1013 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1014 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1020 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1021 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1027 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1028 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1034 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1035 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1041 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1042 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1048 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1049 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1055 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1056 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1062 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1063 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1069 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1070 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1076 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1077 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1083 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1084 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1090 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1091 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1097 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1098 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1107 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1108 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1114 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1115 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1121 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1122 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1128 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1129 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1135 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1136 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1142 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1143 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1149 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1150 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1156 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1157 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1163 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1164 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1170 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1171 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1177 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1178 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1184 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1185 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1191 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1192 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1198 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1199 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1205 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1206 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1212 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1213 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1479 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1480 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1486 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1487 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1493 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1494 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1500 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1501 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1507 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1508 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1514 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1515 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1521 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1522 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1528 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1529 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1535 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1536 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1545 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1546 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1552 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1553 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1559 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1560 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1566 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1567 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1573 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1574 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1580 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1581 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1587 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1588 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1594 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1595 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1601 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
1602 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
1776 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1777 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1783 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1784 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1790 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1791 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1800 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1801 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1807 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1808 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1814 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1815 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1851 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read fr…
2127 #define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2128 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2134 #define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2135 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2141 #define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2142 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2148 #define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2149 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2155 #define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2156 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2162 #define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2163 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2169 #define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2170 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2176 #define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2177 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2186 #define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2187 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2193 #define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2194 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2200 #define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2201 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2207 #define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2208 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2214 #define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2215 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2221 #define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2222 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2228 #define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2229 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2235 #define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2236 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2242 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
2245 #define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */
2246 #define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */
2248 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
2251 #define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */
2252 #define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */
2254 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
2257 #define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */
2258 #define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */
2260 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
2263 #define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */
2264 #define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */
2266 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
2269 #define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */
2270 #define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */
2272 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
2275 #define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */
2276 #define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */
2278 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
2281 #define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */
2282 #define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */
2284 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
2287 #define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */
2288 #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
2465 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2466 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2472 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2473 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2479 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
2480 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2489 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2490 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2496 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2497 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2503 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
2504 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2510 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
2513 #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */
2514 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */
2516 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
2519 #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */
2520 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */
2522 /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */
2525 #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */
2526 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */
2544 /* Description: Select key slot ID to be read over AHB or pushed over secure APB when TASKS_PUSH_KE…
2546 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_K…
2578 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
2634 #define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */
2666 …n order to write to bits 0-7. Any other value will ignore writes to this register. Read as zero. */
2885 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
2886 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2892 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
2893 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2899 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
2900 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2906 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
2907 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2913 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
2914 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2920 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
2921 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2927 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
2928 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2934 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
2935 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
2941 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
2942 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
2948 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
2949 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
2955 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
2956 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
2962 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
2963 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
2969 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
2970 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
2976 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
2977 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
2983 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
2984 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
2990 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
2991 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
2997 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
2998 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
3004 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
3005 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
3011 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
3012 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
3018 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
3019 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
3025 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
3026 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
3032 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
3033 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
3039 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
3040 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
3046 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
3047 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
3053 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
3054 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
3060 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
3061 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
3067 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
3068 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
3074 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
3075 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
3081 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
3082 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
3088 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
3089 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
3095 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
3096 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
3102 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
3103 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
3112 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
3113 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
3119 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
3120 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
3126 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
3127 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
3133 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
3134 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
3140 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
3141 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
3147 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
3148 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
3154 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
3155 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
3161 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
3162 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
3168 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
3169 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
3175 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
3176 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
3182 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
3183 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
3189 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
3190 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
3196 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
3197 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
3203 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
3204 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
3210 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
3211 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
3217 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
3218 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
3224 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
3225 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
3231 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
3232 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
3238 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
3239 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
3245 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
3246 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
3252 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
3253 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
3259 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
3260 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
3266 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
3267 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
3273 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
3274 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
3280 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
3281 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
3287 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
3288 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
3294 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
3295 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
3301 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
3302 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
3308 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
3309 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
3315 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
3316 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
3322 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
3323 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
3329 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
3330 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
3334 /* Description: Read GPIO port */
3729 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
3730 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
3736 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
3737 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
3743 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
3744 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
3750 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
3751 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
3757 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
3758 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
3764 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
3765 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
3771 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
3772 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
3778 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
3779 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
3785 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
3786 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
3792 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
3793 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
3799 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
3800 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
3806 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
3807 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
3813 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
3814 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
3820 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
3821 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
3827 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
3828 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
3834 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
3835 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
3841 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
3842 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
3848 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
3849 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
3855 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
3856 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
3862 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
3863 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
3869 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
3870 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
3876 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
3877 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
3883 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
3884 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
3890 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
3891 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
3897 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
3898 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
3904 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
3905 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
3911 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
3912 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
3918 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
3919 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
3925 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
3926 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
3932 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
3933 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
3939 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
3940 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
3946 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
3947 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
3956 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
3957 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
3963 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
3964 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
3970 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
3971 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
3977 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
3978 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
3984 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
3985 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
3991 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
3992 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
3998 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
3999 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
4005 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
4006 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
4012 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
4013 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
4019 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
4020 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
4026 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
4027 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
4033 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
4034 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
4040 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
4041 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
4047 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
4048 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
4054 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
4055 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
4061 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
4062 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
4068 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
4069 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
4075 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
4076 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
4082 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
4083 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
4089 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
4090 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
4096 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
4097 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
4103 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
4104 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
4110 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
4111 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
4117 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
4118 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
4124 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
4125 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
4131 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
4132 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
4138 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
4139 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
4145 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
4146 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
4152 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
4153 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
4159 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
4160 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
4166 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
4167 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
4173 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
4174 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
4570 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
4571 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
4577 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4578 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4584 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4585 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4594 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
4595 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
4601 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4602 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4608 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4609 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4857 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4858 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4864 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4865 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4871 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4872 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4881 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4882 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4888 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4889 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4895 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4896 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
5221 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5222 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5228 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5229 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5235 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5236 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5242 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5243 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5249 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5250 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5256 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5257 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5263 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5264 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5273 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5274 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5280 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5281 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5287 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5288 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5294 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5295 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5301 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5302 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5308 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5309 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5315 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5316 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5368 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
5631 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5632 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5638 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5639 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5645 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5646 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5652 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5653 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5659 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5660 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5666 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5667 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5676 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5677 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5683 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5684 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5690 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5691 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5697 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5698 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5704 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5705 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5711 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5712 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5760 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5761 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5767 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5768 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5774 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5775 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5781 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5782 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5788 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5789 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5795 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5796 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5805 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5806 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5812 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5813 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5819 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5820 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5826 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5827 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5833 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5834 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5840 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5841 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
6270 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6271 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6277 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6278 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6284 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6285 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6291 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6292 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6298 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6299 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6305 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6306 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6312 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6313 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6319 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6320 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6326 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6327 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6333 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6334 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6340 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6341 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6347 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6348 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6354 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6355 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6361 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6362 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6368 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6369 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6375 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6376 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6382 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6383 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6389 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6390 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6396 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6397 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6403 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
6404 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
6410 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6411 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6417 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6418 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6427 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6428 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6434 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6435 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6441 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6442 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6448 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6449 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6455 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6456 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6462 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6463 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6469 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6470 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6476 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6477 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6483 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6484 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6490 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6491 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6497 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6498 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6504 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6505 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6511 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6512 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6518 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6519 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6525 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6526 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6532 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6533 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6539 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6540 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6546 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6547 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6553 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6554 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6560 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
6561 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
6567 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6568 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6574 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6575 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6757 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read afte…
6974 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6975 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6981 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
6982 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
6988 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6989 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6995 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
6996 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7002 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7003 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7012 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7013 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7019 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7020 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7026 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7027 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7033 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7034 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7040 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7041 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7188 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer.…
7190 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. …
7321 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7322 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7328 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7329 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7335 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7336 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7345 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7346 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7352 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7353 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7359 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7360 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7380 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
7381 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
7384 /* Bit 0 : TX buffer over-read detected, and prevented */
7387 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
7388 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
7523 /* Description: Over-read character */
7525 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
7626 #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7627 #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7633 #define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7634 #define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7640 #define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
7641 #define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7650 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7651 #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7657 #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7658 #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7664 #define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
7665 #define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
8096 /* Bit 2 : Configure read permissions for flash region n */
8097 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8098 …_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
8099 #define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */
8100 #define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */
8129 /* Bit 2 : Configure read permissions for RAM region n */
8130 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8131 #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ fi…
8132 #define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */
8133 #define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */
8511 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8512 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8518 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8519 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8525 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8526 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8532 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8533 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8539 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8540 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8546 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8547 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8556 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8557 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8563 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8564 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8570 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8571 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8577 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8578 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8584 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8585 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8591 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8592 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8983 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8984 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8990 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8991 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8997 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8998 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9004 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9005 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9011 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9012 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9018 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9019 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9025 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9026 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9035 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
9036 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9042 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
9043 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9049 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9050 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9056 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9057 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9063 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9064 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9070 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9071 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9077 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9078 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9251 /* Description: Prepare the TWI slave to respond to a read command */
9253 /* Bit 0 : Prepare the TWI slave to respond to a read command */
9369 /* Description: Read command received */
9371 /* Bit 0 : Read command received */
9443 /* Description: Publish configuration for event READ */
9451 /* Bits 3..0 : Channel that event READ will publish to. */
9458 /* Bit 14 : Shortcut between event READ and task SUSPEND */
9473 /* Bit 26 : Enable or disable interrupt for event READ */
9474 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
9475 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
9512 /* Bit 26 : Write '1' to enable interrupt for event READ */
9513 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
9514 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
9515 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9516 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9522 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9523 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9529 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9530 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9536 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9537 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9543 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9544 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9550 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9551 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9557 /* Bit 26 : Write '1' to disable interrupt for event READ */
9558 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
9559 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
9560 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
9561 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9567 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
9568 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9574 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9575 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9581 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9582 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9588 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9589 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9595 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9596 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9602 /* Bit 3 : TX buffer over-read detected, and prevented */
9727 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
9729 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
10174 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10175 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10181 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10182 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10188 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10189 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10195 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
10196 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10202 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10203 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10209 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10210 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10216 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10217 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10223 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10224 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10230 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10231 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10237 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
10238 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10244 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
10245 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10254 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10255 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10261 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10262 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10268 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10269 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10275 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
10276 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10282 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10283 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10289 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10290 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10296 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10297 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10303 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10304 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10310 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10311 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10317 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
10318 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10324 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10325 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10329 /* Description: Error source Note : this register is read / write one to clear. */
10334 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
10335 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
10340 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
10341 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
10346 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
10347 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
10352 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
10353 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10511 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
10546 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure
10573           an address range which the CPU can potentially read! */
10585 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read…
10591 …Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
10594 /* Bit 1 : Read permission for key slot */
10595 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
10596 …T_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */
10597 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */
10598 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */
10807 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10808 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10817 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10818 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */