Lines Matching +full:high +full:- +full:frequency
3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
254 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crysta…
1250 #define FICR_INFO_PACKAGE_PACKAGE_CC (0x2000UL) /*!< CCxx - 236 ball wlCSP */
1375 …ollection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1377 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1612 …TE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
1635 /* Description: Inter-IC Sound 0 */
1680 /* Description: The RXD.PTR register has been copied to internal double-buffers.
1683 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
1700 /* Description: The TDX.PTR register has been copied to internal double-buffers.
1703 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
1864 /* Description: Master clock generator frequency. */
1866 /* Bits 31..0 : Master clock generator frequency. */
1915 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
1916 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
1925 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2546 … the KMU is idle or not in use NOTE: Note that index N in UICR->KEYSLOT.KEY[N] and UICR->KEY…
2552 /* Description: Non-volatile memory controller 0 */
2560 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
2584 /* Description: Register for erasing all non-volatile user memory */
2586 … : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by se…
2600 /* Description: I-code cache configuration register */
2615 /* Description: I-code cache hit counter */
2622 /* Description: I-code cache miss counter */
2639 /* Description: Non-secure APPROTECT enable register */
2646 /* Bit 0 : Allow non-secure code to set APPROTECT */
2666 …EY_EnableWrite (0xACCE55UL) /*!< Must be written in order to write to bits 0-7. Any other value wi…
2691 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
2697 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
2703 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
2709 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
2715 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
2721 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
2727 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
2733 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
2739 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
2745 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
2751 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
2757 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
2763 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
2769 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
2775 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
2781 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
2787 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
2793 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
2799 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
2805 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
2811 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
2817 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
2823 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
2829 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
2835 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
2841 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
2847 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
2853 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
2859 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
2865 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
2871 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
2877 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
2886 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2887 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2893 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2894 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2900 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2901 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2907 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2908 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2914 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2915 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2921 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2922 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2928 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2929 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2935 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
2936 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2942 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
2943 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2949 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
2950 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2956 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
2957 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2963 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
2964 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2970 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
2971 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2977 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
2978 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2984 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
2985 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2991 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
2992 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2998 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
2999 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3005 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
3006 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3012 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
3013 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3019 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
3020 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3026 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
3027 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3033 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
3034 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3040 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
3041 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3047 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
3048 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3054 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
3055 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3061 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
3062 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3068 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
3069 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3075 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
3076 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3082 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
3083 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3089 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
3090 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3096 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
3097 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3103 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
3104 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3113 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
3120 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
3127 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
3134 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
3141 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
3148 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
3155 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
3162 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
3169 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
3176 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
3183 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
3190 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
3197 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
3204 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
3211 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
3218 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
3225 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
3232 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
3239 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
3246 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
3253 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
3260 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
3267 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
3274 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
3281 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
3288 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
3295 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
3302 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
3309 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
3316 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
3323 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
3330 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
3340 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
3346 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
3352 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
3358 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
3364 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
3370 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
3376 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
3382 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
3388 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
3394 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
3400 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
3406 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
3412 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
3418 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
3424 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
3430 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
3436 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
3442 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
3448 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
3454 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
3460 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
3466 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
3472 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
3478 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
3484 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
3490 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
3496 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
3502 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
3508 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
3514 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
3520 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
3526 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
4373 /* Description: Select between default DETECT signal behaviour and LDETECT mode (For non-secure pin…
4397 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
4404 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
4405 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
4406 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
4407 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or …
4408 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-…
4409 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-an…
4410 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-…
4624 /* Bits 31..0 : PDM_CLK frequency */
4652 …dule gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) …
4655 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
4665 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
4902 /* Bit 18 : Reset triggered through CTRL-AP */
4908 /* Bit 17 : Reset from CPU lock-up detected */
5331 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
5334 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
5335 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
5371 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
5372 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word i…
5373 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
5374 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
5440 /* Description: Power-fail comparator configuration */
5442 /* Bits 4..1 : Power-fail comparator threshold setting */
5456 /* Bit 0 : Enable or disable power-fail comparator */
5473 /* Description: Real-time counter 0 */
5852 /* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when …
5886 /* Description: Stop the ADC and terminate any on-going conversion */
5888 /* Bit 0 : Stop the ADC and terminate any on-going conversion */
5894 /* Description: Starts offset auto-calibration */
5896 /* Bit 0 : Starts offset auto-calibration */
6008 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
6010 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
6584 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
6677 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
6678 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
6685 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
6686 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
6690 /* Description: Description cluster: High/low limits for event monitoring a channel */
6692 /* Bits 31..16 : High level limit */
6693 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
6694 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. …
6712 … combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher…
7093 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
7096 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
7097 …Y_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
7172 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7188 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer.…
7190 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. …
7384 /* Bit 0 : TX buffer over-read detected, and prevented */
7500 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7523 /* Description: Over-read character */
7525 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
7689 #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-…
7692 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
7695 …cure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set …
7697 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute f…
7700 /* Description: Description cluster: Select between secure and non-secure attribute for the DPPI c…
7705 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */
7711 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */
7717 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */
7723 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */
7729 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */
7735 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */
7741 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */
7747 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */
7753 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */
7759 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */
7765 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */
7771 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */
7777 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */
7783 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */
7789 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */
7795 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */
7808 /* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to …
7813 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */
7819 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */
7825 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */
7831 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */
7837 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */
7843 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */
7849 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */
7855 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */
7861 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */
7867 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */
7873 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */
7879 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */
7885 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */
7891 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */
7897 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */
7903 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */
7909 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */
7915 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */
7921 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */
7927 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */
7933 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */
7939 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */
7945 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */
7951 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */
7957 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */
7963 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */
7969 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */
7975 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */
7981 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */
7987 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */
7993 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */
7999 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */
8012 /* Description: Description cluster: Define which flash region can contain the non-secure callable …
8025 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
8033 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8036 …) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (se…
8037 …FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte siz…
8038 …FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte siz…
8039 …ASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte siz…
8040 …ASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte siz…
8041 …ASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte siz…
8042 …SHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte si…
8043 …SHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte si…
8044 …SHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte si…
8047 /* Description: Description cluster: Define which RAM region can contain the non-secure callable (N…
8060 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
8068 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8071 …) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (se…
8072 …U_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte siz…
8073 …U_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte siz…
8074 …RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte siz…
8075 …RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte siz…
8076 …RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte siz…
8077 …AMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte si…
8078 …AMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte si…
8079 …AMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte si…
8093 …U_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */
8126 #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-sec…
8165 …NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set …
8171 …ble: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Perip…
8181 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
8184 …CUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
8186 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute fo…
8187 …plit (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attr…
8315 /* Description: Deprecated register - Shut down timer */
8317 /* Bit 0 : Deprecated field - Shut down timer */
8383 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
8602 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
8632 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
9138 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
9140 /* Bits 31..0 : TWI master clock frequency */
9141 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9142 …Y_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9216 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
9602 /* Bit 3 : TX buffer over-read detected, and prevented */
9727 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
9729 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
9852 /* Description: CTS is deactivated (set high). Not Clear To Send. */
9854 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
10570 …ion cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
10572 APB mapped write-only key registers, else the KMU can push this key value into
10580 …iption cluster: Define permissions for the key slot with ID=n+1. Bits 0-15 and 16-31 can only be w…
10963 /*lint --flb "Leave library region" */