Lines Matching full:enable

80 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
93 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
106 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
119 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
150 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
163 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
170 /* Description: Enable or disable interrupt */
172 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
176 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
178 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
182 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
185 /* Description: Enable interrupt */
187 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
192 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
194 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
199 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
306 /* Description: Enable CRYPTOCELL subsystem */
308 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
309 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
310 …PTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
353 /* Bit 0 : Enable or disable the ERASEALL mechanism */
371 /* Description: Description cluster: Enable channel group n */
373 /* Bit 0 : Enable channel group n */
393 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
406 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
413 /* Description: Channel enable register */
415 /* Bit 15 : Enable or disable channel 15 */
419 #define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
421 /* Bit 14 : Enable or disable channel 14 */
425 #define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
427 /* Bit 13 : Enable or disable channel 13 */
431 #define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
433 /* Bit 12 : Enable or disable channel 12 */
437 #define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
439 /* Bit 11 : Enable or disable channel 11 */
443 #define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
445 /* Bit 10 : Enable or disable channel 10 */
449 #define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
451 /* Bit 9 : Enable or disable channel 9 */
455 #define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
457 /* Bit 8 : Enable or disable channel 8 */
461 #define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
463 /* Bit 7 : Enable or disable channel 7 */
467 #define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
469 /* Bit 6 : Enable or disable channel 6 */
473 #define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
475 /* Bit 5 : Enable or disable channel 5 */
479 #define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
481 /* Bit 4 : Enable or disable channel 4 */
485 #define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
487 /* Bit 3 : Enable or disable channel 3 */
491 #define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
493 /* Bit 2 : Enable or disable channel 2 */
497 #define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
499 /* Bit 1 : Enable or disable channel 1 */
503 #define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
505 /* Bit 0 : Enable or disable channel 0 */
509 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
512 /* Description: Channel enable set register */
514 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
519 #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
521 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
526 #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
528 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
533 #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
535 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
540 #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
542 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
547 #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
549 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
554 #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
556 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
561 #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
563 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
568 #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
570 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
575 #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
577 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
582 #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
584 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
589 #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
591 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
596 #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
598 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
603 #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
605 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
610 #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
612 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
617 #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
619 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
624 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
627 /* Description: Channel enable clear register */
629 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
636 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
643 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
650 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
657 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
664 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
671 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
678 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
685 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
692 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
699 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
706 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
713 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
720 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
727 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
734 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
859 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
881 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
888 /* Description: Enable or disable interrupt */
890 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
894 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
896 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
900 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
902 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
906 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
908 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
912 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
914 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
918 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
920 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
924 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
926 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
930 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
932 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
936 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
938 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
942 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
944 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
948 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
950 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
954 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
956 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
960 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
962 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
966 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
968 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
972 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
974 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
978 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
980 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
984 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
987 /* Description: Enable interrupt */
989 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
994 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
996 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1001 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1003 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1008 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1010 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1015 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1017 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1022 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1024 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1029 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1031 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1036 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1038 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1043 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1045 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1050 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1052 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1057 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1059 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1064 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1066 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1071 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1073 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1078 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1080 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1085 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1087 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1092 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1094 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1099 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1397 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
1410 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
1423 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
1454 #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
1467 #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
1474 /* Description: Enable interrupt */
1476 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1481 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1483 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
1488 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1490 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
1495 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1497 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
1502 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1504 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
1509 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1511 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
1516 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1518 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1523 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1525 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
1530 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1532 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
1537 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
1660 #define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
1673 #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
1717 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1730 #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
1743 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1750 /* Description: Enable or disable interrupt */
1752 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
1756 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
1758 /* Bit 2 : Enable or disable interrupt for event STOPPED */
1762 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
1764 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
1768 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
1771 /* Description: Enable interrupt */
1773 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
1778 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
1780 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
1785 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
1787 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
1792 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
1819 /* Description: Enable I2S module. */
1821 /* Bit 0 : Enable I2S module. */
1822 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1823 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1825 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
1837 /* Description: Reception (RX) enable. */
1839 /* Bit 0 : Reception (RX) enable. */
1846 /* Description: Transmission (TX) enable. */
1848 /* Bit 0 : Transmission (TX) enable. */
1855 /* Description: Master clock generator enable. */
1857 /* Bit 0 : Master clock generator enable. */
1928 /* Description: Enable channels. */
1930 /* Bits 1..0 : Enable channels. */
2042 #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
2064 #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
2071 /* Description: Enable or disable interrupt */
2073 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
2077 #define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */
2079 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
2083 #define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */
2085 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
2089 #define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */
2091 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
2095 #define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */
2097 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
2101 #define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */
2103 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
2107 #define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */
2109 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
2113 #define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */
2115 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
2119 #define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */
2122 /* Description: Enable interrupt */
2124 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
2129 #define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */
2131 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
2136 #define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */
2138 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
2143 #define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */
2145 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
2150 #define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */
2152 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
2157 #define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */
2159 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
2164 #define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */
2166 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
2171 #define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */
2173 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
2178 #define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */
2293 /* Bit 7 : Enable broadcasting on channel 7. */
2297 #define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast. */
2299 /* Bit 6 : Enable broadcasting on channel 6. */
2303 #define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast. */
2305 /* Bit 5 : Enable broadcasting on channel 5. */
2309 #define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast. */
2311 /* Bit 4 : Enable broadcasting on channel 4. */
2315 #define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast. */
2317 /* Bit 3 : Enable broadcasting on channel 3. */
2321 #define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast. */
2323 /* Bit 2 : Enable broadcasting on channel 2. */
2327 #define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast. */
2329 /* Bit 1 : Enable broadcasting on channel 1. */
2333 #define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast. */
2335 /* Bit 0 : Enable broadcasting on channel 0. */
2339 #define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast. */
2344 /* Bit 7 : Enable subscription to channel 7. */
2348 #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events. */
2350 /* Bit 6 : Enable subscription to channel 6. */
2354 #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events. */
2356 /* Bit 5 : Enable subscription to channel 5. */
2360 #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events. */
2362 /* Bit 4 : Enable subscription to channel 4. */
2366 #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events. */
2368 /* Bit 3 : Enable subscription to channel 3. */
2372 #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events. */
2374 /* Bit 2 : Enable subscription to channel 2. */
2378 #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events. */
2380 /* Bit 1 : Enable subscription to channel 1. */
2384 #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events. */
2386 /* Bit 0 : Enable subscription to channel 0. */
2390 #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events. */
2439 /* Description: Enable or disable interrupt */
2441 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
2445 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */
2447 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
2451 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */
2453 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
2457 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */
2460 /* Description: Enable interrupt */
2462 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
2467 #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */
2469 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
2474 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */
2476 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
2481 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */
2602 /* Bit 8 : Cache profiling enable */
2606 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
2608 /* Bit 0 : Cache enable */
2612 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
2639 /* Description: Non-secure APPROTECT enable register */
4458 #define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
4471 #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
4511 #define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
4524 #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
4537 #define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
4544 /* Description: Enable or disable interrupt */
4546 /* Bit 2 : Enable or disable interrupt for event END */
4550 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
4552 /* Bit 1 : Enable or disable interrupt for event STOPPED */
4556 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
4558 /* Bit 0 : Enable or disable interrupt for event STARTED */
4562 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4565 /* Description: Enable interrupt */
4567 /* Bit 2 : Write '1' to enable interrupt for event END */
4572 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
4574 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
4579 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
4581 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
4586 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
4613 /* Description: PDM module enable register */
4615 /* Bit 0 : Enable or disable PDM module */
4616 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
4617 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
4619 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
4723 /* Description: Enable constant latency mode. */
4725 /* Bit 0 : Enable constant latency mode. */
4731 /* Description: Enable low power mode (variable latency) */
4733 /* Bit 0 : Enable low power mode (variable latency) */
4745 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
4758 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
4798 #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
4811 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
4824 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
4831 /* Description: Enable or disable interrupt */
4833 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
4837 #define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */
4839 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
4843 #define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */
4845 /* Bit 2 : Enable or disable interrupt for event POFWARN */
4849 #define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */
4852 /* Description: Enable interrupt */
4854 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
4859 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
4861 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
4866 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
4868 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
4873 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
4995 #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5008 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */
5021 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */
5079 #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
5092 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
5105 #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */
5118 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */
5131 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */
5144 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
5150 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
5156 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
5162 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
5168 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
5171 /* Description: Enable or disable interrupt */
5173 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
5177 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
5179 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
5183 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
5185 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
5189 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
5191 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
5195 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
5197 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
5201 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
5203 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
5207 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
5209 /* Bit 1 : Enable or disable interrupt for event STOPPED */
5213 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
5216 /* Description: Enable interrupt */
5218 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
5223 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
5225 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
5230 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
5232 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
5237 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
5239 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
5244 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
5246 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
5251 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
5253 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
5258 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
5260 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
5265 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5320 /* Description: PWM module enable register */
5322 /* Bit 0 : Enable or disable PWM module */
5323 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5324 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5326 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5434 /* Bit 0 : Enable System OFF mode */
5437 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */
5456 /* Bit 0 : Enable or disable power-fail comparator */
5460 #define REGULATORS_POFCON_POF_Enabled (1UL) /*!< Enable */
5463 /* Description: Enable DC/DC mode of the main voltage regulator */
5465 /* Bit 0 : Enable DC/DC converter */
5514 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5527 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5540 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
5553 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
5593 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
5606 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
5619 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
5626 /* Description: Enable interrupt */
5628 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
5633 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
5635 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
5640 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
5642 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
5647 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
5649 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
5654 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
5656 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
5661 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
5663 /* Bit 0 : Write '1' to enable interrupt for event TICK */
5668 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
5716 /* Description: Enable or disable event routing */
5718 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
5724 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
5730 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
5736 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
5742 /* Bit 1 : Enable or disable event routing for event OVRFLW */
5748 /* Bit 0 : Enable or disable event routing for event TICK */
5755 /* Description: Enable event routing */
5757 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
5762 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
5764 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
5769 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
5771 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
5776 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
5778 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
5783 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
5785 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
5790 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
5792 /* Bit 0 : Write '1' to enable event routing for event TICK */
5797 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
5908 #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5921 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
5934 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5947 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */
6032 #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6045 #define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6058 #define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
6071 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */
6084 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */
6097 #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6110 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */
6123 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */
6130 /* Description: Enable or disable interrupt */
6132 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
6136 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
6138 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
6142 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
6144 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
6148 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
6150 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
6154 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
6156 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
6160 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
6162 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
6166 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
6168 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
6172 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
6174 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
6178 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
6180 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
6184 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
6186 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
6190 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
6192 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
6196 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
6198 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
6202 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
6204 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
6208 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
6210 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
6214 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
6216 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
6220 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
6222 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
6226 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
6228 /* Bit 5 : Enable or disable interrupt for event STOPPED */
6232 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6234 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
6238 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
6240 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
6244 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
6246 /* Bit 2 : Enable or disable interrupt for event DONE */
6250 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
6252 /* Bit 1 : Enable or disable interrupt for event END */
6256 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
6258 /* Bit 0 : Enable or disable interrupt for event STARTED */
6262 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6265 /* Description: Enable interrupt */
6267 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
6272 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
6274 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
6279 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
6281 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
6286 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
6288 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
6293 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
6295 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
6300 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
6302 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
6307 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
6309 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
6314 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
6316 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
6321 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
6323 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
6328 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
6330 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
6335 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
6337 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
6342 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
6344 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
6349 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
6351 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
6356 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
6358 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
6363 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
6365 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
6370 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
6372 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
6377 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
6379 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
6384 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6386 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
6391 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
6393 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
6398 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
6400 /* Bit 2 : Write '1' to enable interrupt for event DONE */
6405 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
6407 /* Bit 1 : Write '1' to enable interrupt for event END */
6412 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
6414 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
6419 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
6588 /* Description: Enable or disable ADC */
6590 /* Bit 0 : Enable or disable ADC */
6591 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6592 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6594 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
6633 /* Bit 24 : Enable burst mode */
6639 /* Bit 20 : Enable differential mode */
6804 #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
6817 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
6830 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
6843 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
6901 #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6914 #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
6927 #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6940 #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
6953 #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6966 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
6969 /* Description: Enable interrupt */
6971 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
6976 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6978 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
6983 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
6985 /* Bit 6 : Write '1' to enable interrupt for event END */
6990 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
6992 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
6997 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
6999 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
7004 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7045 /* Description: Enable SPIM */
7047 /* Bits 3..0 : Enable or disable SPIM */
7048 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7049 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7051 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
7221 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
7234 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
7274 #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
7287 #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
7300 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
7313 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
7316 /* Description: Enable interrupt */
7318 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
7323 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
7325 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
7330 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7332 /* Bit 1 : Write '1' to enable interrupt for event END */
7337 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
7392 /* Description: Enable SPI slave */
7394 /* Bits 3..0 : Enable or disable SPI slave */
7395 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7396 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7398 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
7567 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7580 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7593 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7600 /* Description: Enable or disable interrupt */
7602 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
7606 #define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */
7608 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
7612 #define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */
7614 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */
7618 #define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */
7621 /* Description: Enable interrupt */
7623 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
7628 #define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */
7630 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
7635 #define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */
7637 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
7642 #define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */
8194 /* Description: Enable debug domain and aquire selected GPIOs */
8197 #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8198 #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8200 #define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */
8337 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8350 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8363 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
8376 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
8389 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
8402 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
8424 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
8437 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
8443 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
8449 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
8455 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
8461 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
8467 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
8473 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8479 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8485 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8491 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8497 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8503 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8506 /* Description: Enable interrupt */
8508 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
8513 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
8515 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
8520 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
8522 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
8527 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
8529 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
8534 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
8536 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
8541 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
8543 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
8548 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
8681 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
8694 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
8707 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8720 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
8733 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
8809 #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
8822 #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
8835 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
8848 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8861 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8874 #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
8887 #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
8900 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
8906 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8912 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
8918 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
8924 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8930 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
8933 /* Description: Enable or disable interrupt */
8935 /* Bit 24 : Enable or disable interrupt for event LASTTX */
8939 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
8941 /* Bit 23 : Enable or disable interrupt for event LASTRX */
8945 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
8947 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
8951 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
8953 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
8957 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
8959 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
8963 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
8965 /* Bit 9 : Enable or disable interrupt for event ERROR */
8969 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
8971 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8975 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8978 /* Description: Enable interrupt */
8980 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
8985 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
8987 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
8992 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
8994 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
8999 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9001 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9006 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9008 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
9013 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
9015 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9020 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
9022 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9027 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9103 /* Description: Enable TWIM */
9105 /* Bits 3..0 : Enable or disable TWIM */
9106 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9107 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9109 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
9265 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9278 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
9291 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
9304 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
9317 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
9384 #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
9397 #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
9410 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9423 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9436 #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
9449 #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
9462 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9468 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9471 /* Description: Enable or disable interrupt */
9473 /* Bit 26 : Enable or disable interrupt for event READ */
9477 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
9479 /* Bit 25 : Enable or disable interrupt for event WRITE */
9483 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
9485 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9489 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9491 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9495 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9497 /* Bit 9 : Enable or disable interrupt for event ERROR */
9501 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9503 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9507 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9510 /* Description: Enable interrupt */
9512 /* Bit 26 : Write '1' to enable interrupt for event READ */
9517 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
9519 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
9524 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
9526 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9531 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9533 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9538 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9540 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9545 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
9547 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9552 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9628 /* Description: Enable TWIS */
9630 /* Bits 3..0 : Enable or disable TWIS */
9631 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9632 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9634 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
9714 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9720 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
9784 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
9797 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
9810 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
9823 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
9836 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
9948 #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
9961 #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
9974 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
9987 #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
10000 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
10013 #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
10026 #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
10039 #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
10052 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10065 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10078 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
10091 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
10097 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10100 /* Description: Enable or disable interrupt */
10102 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
10106 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
10108 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
10112 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
10114 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
10118 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
10120 /* Bit 17 : Enable or disable interrupt for event RXTO */
10124 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
10126 /* Bit 9 : Enable or disable interrupt for event ERROR */
10130 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
10132 /* Bit 8 : Enable or disable interrupt for event ENDTX */
10136 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
10138 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
10142 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
10144 /* Bit 4 : Enable or disable interrupt for event ENDRX */
10148 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
10150 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
10154 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
10156 /* Bit 1 : Enable or disable interrupt for event NCTS */
10160 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
10162 /* Bit 0 : Enable or disable interrupt for event CTS */
10166 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
10169 /* Description: Enable interrupt */
10171 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
10176 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
10178 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
10183 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10185 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10190 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10192 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
10197 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
10199 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10204 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
10206 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
10211 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10213 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
10218 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
10220 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
10225 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10227 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10232 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
10234 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
10239 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
10241 /* Bit 0 : Write '1' to enable interrupt for event CTS */
10246 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
10356 /* Description: Enable UART */
10358 /* Bits 3..0 : Enable or disable UARTE */
10359 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10360 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10362 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
10592 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over…
10598 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */
10604 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */
10773 #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
10795 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
10802 /* Description: Enable interrupt */
10804 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
10809 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
10889 /* Description: Enable register for reload request registers */
10891 /* Bit 7 : Enable or disable RR[7] register */
10895 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
10897 /* Bit 6 : Enable or disable RR[6] register */
10901 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
10903 /* Bit 5 : Enable or disable RR[5] register */
10907 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
10909 /* Bit 4 : Enable or disable RR[4] register */
10913 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
10915 /* Bit 3 : Enable or disable RR[3] register */
10919 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
10921 /* Bit 2 : Enable or disable RR[2] register */
10925 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
10927 /* Bit 1 : Enable or disable RR[1] register */
10931 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
10933 /* Bit 0 : Enable or disable RR[0] register */
10937 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */