Lines Matching full:disable

79 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
92 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
105 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
118 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
149 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
162 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
170 /* Description: Enable or disable interrupt */
172 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
175 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */
178 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
181 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */
202 /* Description: Disable interrupt */
204 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
209 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
211 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
216 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
308 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
353 /* Bit 0 : Enable or disable the ERASEALL mechanism */
379 /* Description: Description cluster: Disable channel group n */
381 /* Bit 0 : Disable channel group n */
392 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
405 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
415 /* Bit 15 : Enable or disable channel 15 */
418 #define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
421 /* Bit 14 : Enable or disable channel 14 */
424 #define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
427 /* Bit 13 : Enable or disable channel 13 */
430 #define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
433 /* Bit 12 : Enable or disable channel 12 */
436 #define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
439 /* Bit 11 : Enable or disable channel 11 */
442 #define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
445 /* Bit 10 : Enable or disable channel 10 */
448 #define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
451 /* Bit 9 : Enable or disable channel 9 */
454 #define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
457 /* Bit 8 : Enable or disable channel 8 */
460 #define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
463 /* Bit 7 : Enable or disable channel 7 */
466 #define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
469 /* Bit 6 : Enable or disable channel 6 */
472 #define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
475 /* Bit 5 : Enable or disable channel 5 */
478 #define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
481 /* Bit 4 : Enable or disable channel 4 */
484 #define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
487 /* Bit 3 : Enable or disable channel 3 */
490 #define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
493 /* Bit 2 : Enable or disable channel 2 */
496 #define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
499 /* Bit 1 : Enable or disable channel 1 */
502 #define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
505 /* Bit 0 : Enable or disable channel 0 */
508 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
634 #define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
641 #define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
648 #define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
655 #define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
662 #define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
669 #define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
676 #define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
683 #define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
690 #define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
697 #define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
704 #define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
711 #define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
718 #define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
725 #define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
732 #define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
739 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
858 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
880 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
888 /* Description: Enable or disable interrupt */
890 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
893 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
896 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
899 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
902 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
905 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
908 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
911 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
914 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
917 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
920 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
923 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
926 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
929 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
932 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
935 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
938 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
941 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
944 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
947 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
950 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
953 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
956 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
959 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
962 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
965 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
968 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
971 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
974 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
977 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
980 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
983 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1102 /* Description: Disable interrupt */
1104 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1109 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1111 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1116 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1118 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1123 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1125 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1130 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1132 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1137 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1139 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1144 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1146 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1151 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1153 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1158 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1160 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1165 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1167 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1172 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1174 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1179 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1181 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1186 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1188 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1193 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1195 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1200 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1202 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1207 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1209 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1214 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1396 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */
1409 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */
1422 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */
1453 #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */
1466 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */
1540 /* Description: Disable interrupt */
1542 /* Bit 31 : Write '1' to disable interrupt for event PORT */
1547 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1549 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
1554 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1556 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
1561 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1563 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
1568 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1570 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
1575 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
1577 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
1582 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
1584 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
1589 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
1591 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
1596 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
1598 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
1603 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
1659 #define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
1672 #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
1716 #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
1729 #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
1742 #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
1750 /* Description: Enable or disable interrupt */
1752 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
1755 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
1758 /* Bit 2 : Enable or disable interrupt for event STOPPED */
1761 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
1764 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
1767 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
1795 /* Description: Disable interrupt */
1797 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
1802 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
1804 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
1809 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
1811 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
1816 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
1824 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2041 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */
2063 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */
2071 /* Description: Enable or disable interrupt */
2073 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
2076 #define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */
2079 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
2082 #define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */
2085 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
2088 #define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */
2091 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
2094 #define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */
2097 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
2100 #define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */
2103 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
2106 #define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */
2109 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
2112 #define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */
2115 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
2118 #define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */
2181 /* Description: Disable interrupt */
2183 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
2188 #define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */
2190 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
2195 #define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */
2197 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
2202 #define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */
2204 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
2209 #define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */
2211 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
2216 #define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */
2218 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
2223 #define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */
2225 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
2230 #define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */
2232 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
2237 #define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */
2296 #define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast. */
2302 #define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast. */
2308 #define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast. */
2314 #define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast. */
2320 #define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast. */
2326 #define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast. */
2332 #define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast. */
2338 #define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast. */
2347 #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events. */
2353 #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events. */
2359 #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events. */
2365 #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events. */
2371 #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events. */
2377 #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events. */
2383 #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events. */
2389 #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events. */
2439 /* Description: Enable or disable interrupt */
2441 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
2444 #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */
2447 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
2450 #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */
2453 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
2456 #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */
2484 /* Description: Disable interrupt */
2486 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
2491 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */
2493 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
2498 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */
2500 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
2505 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */
2605 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
2611 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
4457 #define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
4470 #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
4510 #define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
4523 #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
4536 #define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
4544 /* Description: Enable or disable interrupt */
4546 /* Bit 2 : Enable or disable interrupt for event END */
4549 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
4552 /* Bit 1 : Enable or disable interrupt for event STOPPED */
4555 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
4558 /* Bit 0 : Enable or disable interrupt for event STARTED */
4561 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4589 /* Description: Disable interrupt */
4591 /* Bit 2 : Write '1' to disable interrupt for event END */
4596 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
4598 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
4603 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
4605 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
4610 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4615 /* Bit 0 : Enable or disable PDM module */
4618 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
4744 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */
4757 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */
4797 #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */
4810 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */
4823 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */
4831 /* Description: Enable or disable interrupt */
4833 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
4836 #define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */
4839 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
4842 #define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */
4845 /* Bit 2 : Enable or disable interrupt for event POFWARN */
4848 #define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */
4876 /* Description: Disable interrupt */
4878 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
4883 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
4885 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
4890 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
4892 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
4897 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
4994 #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5007 #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */
5020 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */
5078 #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
5091 #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
5104 #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */
5117 #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */
5130 #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */
5143 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
5149 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
5155 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
5161 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
5167 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
5171 /* Description: Enable or disable interrupt */
5173 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
5176 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
5179 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
5182 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
5185 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
5188 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
5191 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
5194 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
5197 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
5200 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
5203 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
5206 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
5209 /* Bit 1 : Enable or disable interrupt for event STOPPED */
5212 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
5268 /* Description: Disable interrupt */
5270 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
5275 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
5277 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
5282 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
5284 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
5289 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
5291 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
5296 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
5298 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
5303 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
5305 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
5310 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
5312 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
5317 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5322 /* Bit 0 : Enable or disable PWM module */
5456 /* Bit 0 : Enable or disable power-fail comparator */
5459 #define REGULATORS_POFCON_POF_Disabled (0UL) /*!< Disable */
5513 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5526 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5539 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
5552 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
5592 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
5605 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
5618 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
5671 /* Description: Disable interrupt */
5673 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
5678 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5680 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
5685 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5687 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
5692 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5694 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
5699 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5701 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
5706 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5708 /* Bit 0 : Write '1' to disable interrupt for event TICK */
5713 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
5716 /* Description: Enable or disable event routing */
5718 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
5721 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
5722 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
5724 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
5727 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
5728 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
5730 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
5733 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
5734 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
5736 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
5739 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
5740 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
5742 /* Bit 1 : Enable or disable event routing for event OVRFLW */
5745 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
5746 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
5748 /* Bit 0 : Enable or disable event routing for event TICK */
5751 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
5752 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
5800 /* Description: Disable event routing */
5802 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
5807 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5809 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
5814 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5816 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
5821 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5823 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
5828 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5830 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
5835 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5837 /* Bit 0 : Write '1' to disable event routing for event TICK */
5842 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
5907 #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5920 #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
5933 #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5946 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */
6031 #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
6044 #define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
6057 #define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
6070 #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */
6083 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */
6096 #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6109 #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */
6122 #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */
6130 /* Description: Enable or disable interrupt */
6132 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
6135 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
6138 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
6141 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
6144 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
6147 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
6150 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
6153 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
6156 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
6159 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
6162 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
6165 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
6168 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
6171 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
6174 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
6177 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
6180 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
6183 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
6186 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
6189 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
6192 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
6195 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
6198 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
6201 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
6204 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
6207 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
6210 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
6213 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
6216 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
6219 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
6222 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
6225 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
6228 /* Bit 5 : Enable or disable interrupt for event STOPPED */
6231 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6234 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
6237 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
6240 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
6243 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
6246 /* Bit 2 : Enable or disable interrupt for event DONE */
6249 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
6252 /* Bit 1 : Enable or disable interrupt for event END */
6255 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
6258 /* Bit 0 : Enable or disable interrupt for event STARTED */
6261 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6422 /* Description: Disable interrupt */
6424 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
6429 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
6431 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
6436 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
6438 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
6443 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
6445 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
6450 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
6452 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
6457 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
6459 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
6464 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
6466 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
6471 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
6473 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
6478 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
6480 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
6485 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
6487 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
6492 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
6494 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
6499 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
6501 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
6506 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
6508 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
6513 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
6515 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
6520 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
6522 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
6527 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
6529 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
6534 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
6536 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
6541 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6543 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
6548 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
6550 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
6555 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
6557 /* Bit 2 : Write '1' to disable interrupt for event DONE */
6562 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
6564 /* Bit 1 : Write '1' to disable interrupt for event END */
6569 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
6571 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
6576 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6588 /* Description: Enable or disable ADC */
6590 /* Bit 0 : Enable or disable ADC */
6593 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
6803 #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
6816 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
6829 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
6842 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
6900 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6913 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
6926 #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
6939 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
6952 #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
6965 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
7007 /* Description: Disable interrupt */
7009 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
7014 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7016 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
7021 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
7023 /* Bit 6 : Write '1' to disable interrupt for event END */
7028 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
7030 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7035 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7037 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
7042 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7047 /* Bits 3..0 : Enable or disable SPIM */
7050 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
7133 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7163 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7220 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */
7233 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */
7273 #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
7286 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
7299 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */
7312 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
7340 /* Description: Disable interrupt */
7342 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
7347 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
7349 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7354 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7356 /* Bit 1 : Write '1' to disable interrupt for event END */
7361 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
7394 /* Bits 3..0 : Enable or disable SPI slave */
7397 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
7566 #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7579 #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7592 #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7600 /* Description: Enable or disable interrupt */
7602 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
7605 #define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */
7608 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
7611 #define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */
7614 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */
7617 #define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */
7645 /* Description: Disable interrupt */
7647 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
7652 #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */
7654 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
7659 #define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */
7661 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
7666 #define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */
8199 #define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */
8336 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
8349 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8362 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
8375 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
8388 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
8401 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
8423 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
8436 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
8442 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
8448 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
8454 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
8460 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
8466 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
8472 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8478 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8484 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8490 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8496 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8502 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8551 /* Description: Disable interrupt */
8553 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
8558 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
8560 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
8565 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
8567 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
8572 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8574 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
8579 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8581 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
8586 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8588 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
8593 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8680 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
8693 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
8706 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8719 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
8732 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
8808 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
8821 #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
8834 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */
8847 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
8860 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
8873 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */
8886 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */
8899 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
8905 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8911 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
8917 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
8923 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8929 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
8933 /* Description: Enable or disable interrupt */
8935 /* Bit 24 : Enable or disable interrupt for event LASTTX */
8938 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
8941 /* Bit 23 : Enable or disable interrupt for event LASTRX */
8944 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
8947 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
8950 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
8953 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
8956 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
8959 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
8962 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
8965 /* Bit 9 : Enable or disable interrupt for event ERROR */
8968 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
8971 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8974 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9030 /* Description: Disable interrupt */
9032 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
9037 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
9039 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
9044 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
9046 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9051 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9053 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9058 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9060 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
9065 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
9067 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9072 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9074 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9079 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9105 /* Bits 3..0 : Enable or disable TWIM */
9108 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
9174 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9204 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9264 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
9277 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
9290 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
9303 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */
9316 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */
9383 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
9396 #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
9409 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
9422 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
9435 #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */
9448 #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */
9461 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9467 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9471 /* Description: Enable or disable interrupt */
9473 /* Bit 26 : Enable or disable interrupt for event READ */
9476 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
9479 /* Bit 25 : Enable or disable interrupt for event WRITE */
9482 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
9485 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9488 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9491 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9494 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9497 /* Bit 9 : Enable or disable interrupt for event ERROR */
9500 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9503 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9506 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9555 /* Description: Disable interrupt */
9557 /* Bit 26 : Write '1' to disable interrupt for event READ */
9562 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
9564 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
9569 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
9571 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9576 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9578 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9583 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9585 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9590 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9592 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9597 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9630 /* Bits 3..0 : Enable or disable TWIS */
9633 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
9714 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9720 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
9783 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
9796 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */
9809 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
9822 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */
9835 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */
9947 #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */
9960 #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */
9973 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
9986 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
9999 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
10012 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
10025 #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
10038 #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */
10051 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10064 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10077 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
10090 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
10096 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
10100 /* Description: Enable or disable interrupt */
10102 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
10105 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
10108 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
10111 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
10114 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
10117 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
10120 /* Bit 17 : Enable or disable interrupt for event RXTO */
10123 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
10126 /* Bit 9 : Enable or disable interrupt for event ERROR */
10129 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
10132 /* Bit 8 : Enable or disable interrupt for event ENDTX */
10135 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
10138 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
10141 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
10144 /* Bit 4 : Enable or disable interrupt for event ENDRX */
10147 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
10150 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
10153 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
10156 /* Bit 1 : Enable or disable interrupt for event NCTS */
10159 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
10162 /* Bit 0 : Enable or disable interrupt for event CTS */
10165 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
10249 /* Description: Disable interrupt */
10251 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
10256 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
10258 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10263 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10265 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10270 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10272 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
10277 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
10279 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10284 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10286 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
10291 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10293 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
10298 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
10300 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
10305 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10307 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10312 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
10314 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
10319 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
10321 /* Bit 0 : Write '1' to disable interrupt for event CTS */
10326 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
10358 /* Bits 3..0 : Enable or disable UARTE */
10361 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
10591 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers ov…
10597 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */
10603 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers…
10772 #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
10794 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */
10812 /* Description: Disable interrupt */
10814 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
10819 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
10891 /* Bit 7 : Enable or disable RR[7] register */
10894 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
10897 /* Bit 6 : Enable or disable RR[6] register */
10900 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
10903 /* Bit 5 : Enable or disable RR[5] register */
10906 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
10909 /* Bit 4 : Enable or disable RR[4] register */
10912 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
10915 /* Bit 3 : Enable or disable RR[3] register */
10918 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
10921 /* Bit 2 : Enable or disable RR[2] register */
10924 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
10927 /* Bit 1 : Enable or disable RR[1] register */
10930 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
10933 /* Bit 0 : Enable or disable RR[0] register */
10936 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */