Lines Matching full:write

44 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
51 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
58 /* Bit 0 : Write '1' to Enable interrupt for END event */
68 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
75 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
82 /* Bit 0 : Write '1' to Disable interrupt for END event */
140 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
146 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
152 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
158 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
164 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
170 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
176 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
182 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
188 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
194 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
200 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
206 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
212 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
218 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
224 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
230 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
236 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
242 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
248 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
254 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
260 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
266 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
272 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
278 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
284 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
290 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
296 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
302 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
308 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
314 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
320 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
326 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
335 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
341 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
347 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
353 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
359 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
365 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
371 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
377 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
383 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
389 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
395 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
401 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
407 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
413 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
419 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
425 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
431 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
437 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
443 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
449 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
455 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
461 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
467 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
473 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
479 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
485 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
491 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
497 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
503 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
509 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
515 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
521 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
539 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
545 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
551 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
557 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
563 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
569 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
575 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
581 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
587 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
593 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
599 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
605 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
611 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
617 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
623 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
629 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
635 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
641 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
647 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
653 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
659 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
665 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
671 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
677 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
683 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
689 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
695 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
701 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
707 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
713 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
719 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
725 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
734 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
740 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
746 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
752 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
758 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
764 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
770 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
776 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
782 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
788 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
794 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
800 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
806 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
812 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
818 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
824 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
830 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
836 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
842 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
848 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
854 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
860 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
866 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
872 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
878 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
884 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
890 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
896 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
902 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
908 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
914 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
920 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
942 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
949 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
956 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
966 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
973 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
980 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
1061 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
1068 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
1075 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
1082 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
1092 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
1099 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
1106 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
1113 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
1293 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
1300 /* Bit 2 : Write '1' to Enable interrupt for UP event */
1307 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
1314 /* Bit 0 : Write '1' to Enable interrupt for READY event */
1324 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
1331 /* Bit 2 : Write '1' to Disable interrupt for UP event */
1338 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
1345 /* Bit 0 : Write '1' to Disable interrupt for READY event */
1466 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
1473 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
1483 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
1490 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
1610 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
1617 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
1624 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
1631 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
1638 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
1645 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
1652 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
1659 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
1666 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
1673 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
1680 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
1687 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
1694 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
1701 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
1708 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
1715 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
1725 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
1732 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
1739 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
1746 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
1753 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
1760 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
1767 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
1774 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
1781 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
1788 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
1795 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
1802 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
1809 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
1816 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
1823 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
1830 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
2151 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
2158 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
2165 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
2172 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
2179 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
2186 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
2193 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
2200 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
2207 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
2217 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
2224 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
2231 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
2238 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
2245 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
2252 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
2259 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
2266 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
2273 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
2336 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
2343 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
2350 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
2360 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
2367 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
2374 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
2631 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
2638 /* Bit 2 : Write '1' to Enable interrupt for UP event */
2645 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
2652 /* Bit 0 : Write '1' to Enable interrupt for READY event */
2662 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
2669 /* Bit 2 : Write '1' to Disable interrupt for UP event */
2676 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
2683 /* Bit 0 : Write '1' to Disable interrupt for READY event */
2856 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
2863 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
2870 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
2877 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
2884 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
2891 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
2898 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
2905 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
2912 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
2919 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
2926 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
2933 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
2943 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
2950 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
2957 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
2964 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
2971 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
2978 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
2985 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
2992 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
2999 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
3006 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
3013 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
3020 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
3105 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
3112 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
3119 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
3126 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
3133 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
3140 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
3147 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
3154 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
3161 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
3168 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
3175 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
3182 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
3192 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
3199 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
3206 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
3213 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
3220 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
3227 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
3234 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
3241 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
3248 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
3255 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
3262 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
3269 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
3277 /* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detect…
3279 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3282 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion…
3283 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion …
3285 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3288 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion…
3289 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion …
3291 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3294 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion…
3295 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion …
3297 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3300 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion…
3301 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion …
3303 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3306 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion…
3307 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion …
3309 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3312 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion…
3313 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion …
3315 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3318 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion…
3319 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion …
3321 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3324 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion…
3325 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion …
3327 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3330 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion…
3331 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion …
3333 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3336 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion…
3337 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion …
3339 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3342 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion…
3343 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion …
3345 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3348 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion…
3349 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion …
3351 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3354 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion…
3355 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion …
3357 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3360 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion…
3361 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion …
3363 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3366 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion…
3367 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion …
3369 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3372 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion…
3373 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion …
3375 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3378 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion…
3379 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion …
3381 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3384 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion…
3385 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion …
3387 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3390 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion…
3391 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion …
3393 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3396 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion…
3397 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion …
3399 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3402 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion…
3403 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion …
3405 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3408 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion…
3409 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion …
3411 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3414 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion …
3415 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3417 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3420 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion …
3421 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3423 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3426 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion …
3427 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3429 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3432 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion …
3433 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3435 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3438 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion …
3439 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3441 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3444 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion …
3445 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3447 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3450 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion …
3451 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3453 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3456 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion …
3457 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3459 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3462 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion …
3463 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3465 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3468 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion …
3469 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3474 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3480 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3486 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3492 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3498 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3504 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3510 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3516 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3522 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3528 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3534 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3540 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3546 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3552 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3558 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3564 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3570 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3576 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3582 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3588 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3594 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3600 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3606 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3612 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3618 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3624 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3630 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3636 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3642 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3648 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3654 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3660 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3675 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3678 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3679 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3687 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3690 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3691 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3699 /* Bit 6 : Enable/disable write access watch in region[3] */
3702 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3703 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3711 /* Bit 4 : Enable/disable write access watch in region[2] */
3714 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3715 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3723 /* Bit 2 : Enable/disable write access watch in region[1] */
3726 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3727 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3735 /* Bit 0 : Enable/disable write access watch in region[0] */
3738 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3739 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3751 /* Bit 26 : Enable write access watch in PREGION[1] */
3754 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3755 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3756 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3765 /* Bit 24 : Enable write access watch in PREGION[0] */
3768 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3769 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3770 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3779 /* Bit 6 : Enable write access watch in region[3] */
3782 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3783 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3784 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3793 /* Bit 4 : Enable write access watch in region[2] */
3796 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3797 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3798 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3807 /* Bit 2 : Enable write access watch in region[1] */
3810 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3811 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3812 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3821 /* Bit 0 : Enable write access watch in region[0] */
3824 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3825 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3826 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3838 /* Bit 26 : Disable write access watch in PREGION[1] */
3841 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3842 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3843 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3852 /* Bit 24 : Disable write access watch in PREGION[0] */
3855 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3856 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3857 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3866 /* Bit 6 : Disable write access watch in region[3] */
3869 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3870 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3871 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3880 /* Bit 4 : Disable write access watch in region[2] */
3883 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3884 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3885 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3894 /* Bit 2 : Disable write access watch in region[1] */
3897 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3898 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3899 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3908 /* Bit 0 : Disable write access watch in region[0] */
3911 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3912 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3913 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
4253 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
4260 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
4267 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
4274 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
4281 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
4288 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
4295 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
4302 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
4309 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
4316 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
4323 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
4330 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
4337 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
4344 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
4351 /* Bit 0 : Write '1' to Enable interrupt for READY event */
4361 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
4368 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
4375 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
4382 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
4389 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
4396 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
4403 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
4410 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
4417 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
4424 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
4431 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
4438 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
4445 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
4452 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
4459 /* Bit 0 : Write '1' to Disable interrupt for READY event */
4729 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
4749 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4755 … strongly recommended to only activate erase and write modes when they are actively used. Enabling…
4759 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
4835 /* Description: Write GPIO port */
5037 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5044 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5051 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5058 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5065 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5072 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5079 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5086 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5093 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5100 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5107 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5114 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5121 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5128 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5135 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5142 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5149 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5156 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5163 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5170 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5177 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5184 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5191 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5198 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5205 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5212 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5219 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5226 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5233 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5240 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5247 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5254 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5264 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5271 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5278 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5285 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5292 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5299 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5306 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5313 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5320 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5327 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5334 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5341 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5348 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5355 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5362 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5369 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5376 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5383 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5390 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5397 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5404 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5411 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5418 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5425 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5432 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5439 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5446 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5453 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5460 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5467 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5474 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5481 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5881 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5888 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5895 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5902 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5909 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5916 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5923 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5930 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5937 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5944 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5951 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5958 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5965 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5972 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5979 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5986 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5993 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6000 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6007 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6014 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6021 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6028 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6035 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6042 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6049 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6056 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6063 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6070 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6077 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6084 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6091 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6098 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6108 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6115 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6122 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6129 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6136 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6143 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6150 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6157 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6164 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6171 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6178 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6185 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6192 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6199 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6206 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6213 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6220 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6227 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6234 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6241 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6248 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6255 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6262 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6269 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6276 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6283 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6290 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6297 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6304 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6311 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6318 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6325 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6330 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to …
6336 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to …
6342 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to …
6348 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to …
6354 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to …
6360 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to …
6366 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to …
6372 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to …
6378 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to …
6384 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to …
6390 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to …
6396 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to …
6402 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to …
6408 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to …
6414 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to …
6420 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to …
6426 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to …
6432 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to …
6438 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to …
6444 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to …
6450 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to …
6456 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to …
6462 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to cle…
6468 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to cle…
6474 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to cle…
6480 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to cle…
6486 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to cle…
6492 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to cle…
6498 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to cle…
6504 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
6510 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to cle…
6516 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to cle…
6600 /* Bit 2 : Write '1' to Enable interrupt for END event */
6607 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
6614 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
6624 /* Bit 2 : Write '1' to Disable interrupt for END event */
6631 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
6638 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
6726 /* Description: RAM address pointer to write samples to with EasyDMA */
6728 /* Bits 31..0 : Address to write PDM samples to over DMA */
6746 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
6753 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
6760 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
6770 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
6777 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
6784 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
7259 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7266 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7273 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7280 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7287 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
7294 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
7301 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
7308 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
7315 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
7322 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
7329 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
7336 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
7343 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
7350 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
7357 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
7364 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
7371 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
7378 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
7385 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
7392 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
7399 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
7406 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
7413 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
7420 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
7427 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
7434 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
7441 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
7448 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
7455 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
7462 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
7469 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
7476 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
7486 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
7493 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
7500 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
7507 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
7514 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
7521 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
7528 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
7535 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
7542 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
7549 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
7556 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
7563 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
7570 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
7577 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
7584 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
7591 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
7598 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
7605 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
7612 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
7619 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
7626 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
7633 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
7640 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
7647 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
7654 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
7661 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
7668 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
7675 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
7682 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
7689 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
7696 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
7703 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
8006 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
8013 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
8020 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
8027 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
8034 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
8041 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
8048 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
8058 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
8065 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
8072 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
8079 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
8086 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
8093 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
8100 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
8267 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
8274 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
8281 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
8288 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
8295 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
8305 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
8312 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
8319 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
8326 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
8333 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
8540 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
8547 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
8554 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
8561 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
8568 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
8575 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
8582 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
8589 /* Bit 3 : Write '1' to Enable interrupt for END event */
8596 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
8603 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
8610 /* Bit 0 : Write '1' to Enable interrupt for READY event */
8620 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
8627 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
8634 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
8641 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
8648 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
8655 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
8662 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
8669 /* Bit 3 : Write '1' to Disable interrupt for END event */
8676 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
8683 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
8690 /* Bit 0 : Write '1' to Disable interrupt for READY event */
9153 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
9163 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
9193 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
9200 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
9207 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
9214 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
9221 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
9228 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
9238 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
9245 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
9252 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
9259 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
9266 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
9273 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
9322 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
9329 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
9336 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
9343 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
9350 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
9357 /* Bit 0 : Write '1' to Enable event routing for TICK event */
9367 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
9374 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
9381 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
9388 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
9395 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
9402 /* Bit 0 : Write '1' to Disable event routing for TICK event */
9572 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
9579 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
9586 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
9593 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
9600 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
9607 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
9614 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
9621 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
9628 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
9635 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
9642 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
9649 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
9656 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
9663 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
9670 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
9677 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
9684 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
9691 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
9698 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
9705 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
9712 /* Bit 1 : Write '1' to Enable interrupt for END event */
9719 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
9729 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
9736 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
9743 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
9750 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
9757 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
9764 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
9771 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
9778 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
9785 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
9792 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
9799 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
9806 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
9813 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
9820 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
9827 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
9834 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
9841 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
9848 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
9855 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
9862 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
9869 /* Bit 1 : Write '1' to Disable interrupt for END event */
9876 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
10073 /* Bit 2 : Write '1' to Enable interrupt for READY event */
10083 /* Bit 2 : Write '1' to Disable interrupt for READY event */
10188 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
10195 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
10202 /* Bit 6 : Write '1' to Enable interrupt for END event */
10209 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10216 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
10226 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
10233 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
10240 /* Bit 6 : Write '1' to Disable interrupt for END event */
10247 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10254 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
10427 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
10434 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10441 /* Bit 1 : Write '1' to Enable interrupt for END event */
10451 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
10458 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10465 /* Bit 1 : Write '1' to Disable interrupt for END event */
10491 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
10498 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
10645 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
10655 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
10870 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
10877 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
10884 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
10891 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
10898 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
10905 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
10915 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
10922 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
10929 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
10936 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
10943 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
10950 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
11014 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11021 /* Bit 14 : Write '1' to Enable interrupt for BB event */
11028 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11035 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
11042 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
11049 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11059 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11066 /* Bit 14 : Write '1' to Disable interrupt for BB event */
11073 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11080 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
11087 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
11094 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11104 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11109 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11111 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11116 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11123 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
11266 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
11273 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
11280 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11287 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11294 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11301 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11308 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11318 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
11325 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
11332 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11339 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11346 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11353 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11360 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11370 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11376 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11513 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
11528 /* Bit 25 : Enable or disable interrupt for WRITE event */
11529 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11530 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
11561 /* Bit 26 : Write '1' to Enable interrupt for READ event */
11568 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
11569 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11570 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
11575 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11582 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11589 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11596 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11606 /* Bit 26 : Write '1' to Disable interrupt for READ event */
11613 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
11614 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11615 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
11620 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11627 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11634 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11641 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11804 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
11811 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11818 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
11825 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
11832 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
11839 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
11849 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
11856 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11863 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
11870 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
11877 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
11884 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
12104 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
12111 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
12118 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
12125 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
12132 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
12139 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
12146 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
12153 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
12160 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
12167 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
12174 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
12184 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
12191 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
12198 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
12205 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
12212 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
12219 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
12226 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
12233 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
12240 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
12247 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
12254 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
12494 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
12504 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */