Lines Matching full:read

47 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
48 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
54 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
55 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
61 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
62 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
71 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
72 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
78 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
79 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
85 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
86 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
945 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
946 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
952 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
953 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
959 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
960 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
969 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
970 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
976 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
977 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
983 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
984 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
1064 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
1065 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
1071 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
1072 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1078 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1079 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1085 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1086 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1095 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
1096 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
1102 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
1103 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1109 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1110 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1116 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1117 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1296 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1297 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1303 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1304 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1310 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1311 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1317 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1318 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1327 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1328 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1334 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1335 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1341 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1342 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1348 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1349 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1469 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1470 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1476 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1477 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1486 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1487 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1493 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1494 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1613 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1614 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1620 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1621 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1627 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1628 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1634 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1635 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1641 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1642 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1648 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1649 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1655 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1656 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1662 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1663 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1669 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1670 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1676 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1677 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1683 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1684 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1690 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1691 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1697 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1698 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1704 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1705 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1711 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1712 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1718 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1719 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1728 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1729 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1735 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1736 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1742 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1743 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1749 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1750 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1756 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1757 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1763 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1764 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1770 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1771 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1777 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1778 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1784 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1785 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1791 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1792 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1798 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1799 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1805 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1806 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1812 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1813 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1819 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1820 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1826 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1827 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1833 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1834 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
2069 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_L…
2088 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_L…
2107 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_L…
2126 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_L…
2154 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
2155 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2161 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
2162 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2168 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
2169 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2175 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
2176 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2182 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
2183 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2189 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
2190 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2196 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
2197 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2203 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2204 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2210 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2211 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2220 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2221 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2227 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2228 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2234 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2235 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2241 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2242 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2248 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2249 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2255 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2256 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2262 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2263 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2269 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2270 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2276 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2277 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2339 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2340 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2346 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2347 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2353 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2354 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2363 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2364 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2370 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2371 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2377 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2378 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2414 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read fr…
2634 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2635 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2641 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2642 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2648 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2649 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2655 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2656 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2665 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2666 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2672 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2673 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2679 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2680 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2686 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2687 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2859 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2860 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2866 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2867 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2873 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2874 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2880 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2881 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2887 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2888 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2894 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2895 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2901 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2902 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2908 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2909 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2915 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2916 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2922 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2923 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2929 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2930 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2936 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2937 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2946 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2947 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2953 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2954 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2960 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2961 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2967 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2968 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2974 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2975 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2981 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2982 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2988 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2989 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2995 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2996 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3002 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3003 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3009 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3010 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3016 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3017 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3023 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3024 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3108 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3109 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3115 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3116 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3122 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3123 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3129 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3130 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3136 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3137 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3143 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3144 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3150 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3151 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3157 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3158 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3164 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3165 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3171 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3172 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3178 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3179 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3185 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3186 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3195 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3196 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3202 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3203 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3209 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3210 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3216 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3217 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3223 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3224 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3230 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3231 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3237 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3238 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3244 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3245 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3251 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3252 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3258 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3259 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3265 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3266 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3272 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3273 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3472 /* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detecte…
3477 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion …
3478 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3483 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion …
3484 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3489 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion …
3490 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3495 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion …
3496 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3501 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion …
3502 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3507 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion …
3508 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3513 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion …
3514 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3519 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion …
3520 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3525 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion …
3526 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3531 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion …
3532 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3537 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion …
3538 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3543 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion …
3544 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3549 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion …
3550 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3555 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion …
3556 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3561 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion …
3562 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3567 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion …
3568 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3573 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion …
3574 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3579 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion …
3580 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3585 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion …
3586 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3591 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion …
3592 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3597 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion …
3598 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3603 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion …
3604 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3609 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
3610 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3615 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
3616 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3621 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
3622 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3627 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
3628 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3633 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
3634 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3639 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
3640 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3645 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
3646 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3651 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
3652 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3657 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
3658 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3663 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
3664 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3669 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3672 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3673 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3681 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3684 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3685 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3693 /* Bit 7 : Enable/disable read access watch in region[3] */
3696 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3697 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3705 /* Bit 5 : Enable/disable read access watch in region[2] */
3708 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3709 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3717 /* Bit 3 : Enable/disable read access watch in region[1] */
3720 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3721 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3729 /* Bit 1 : Enable/disable read access watch in region[0] */
3732 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3733 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3744 /* Bit 27 : Enable read access watch in PREGION[1] */
3747 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3748 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3749 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3758 /* Bit 25 : Enable read access watch in PREGION[0] */
3761 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3762 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3763 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3772 /* Bit 7 : Enable read access watch in region[3] */
3775 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3776 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3777 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3786 /* Bit 5 : Enable read access watch in region[2] */
3789 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3790 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3791 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3800 /* Bit 3 : Enable read access watch in region[1] */
3803 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3804 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3805 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3814 /* Bit 1 : Enable read access watch in region[0] */
3817 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3818 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3819 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3831 /* Bit 27 : Disable read access watch in PREGION[1] */
3834 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3835 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3836 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3845 /* Bit 25 : Disable read access watch in PREGION[0] */
3848 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3849 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3850 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3859 /* Bit 7 : Disable read access watch in region[3] */
3862 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3863 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3864 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3873 /* Bit 5 : Disable read access watch in region[2] */
3876 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3877 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3878 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3887 /* Bit 3 : Disable read access watch in region[1] */
3890 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3891 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3892 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3901 /* Bit 1 : Disable read access watch in region[0] */
3904 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3905 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3906 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
4256 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4257 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4263 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4264 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4270 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4271 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4277 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4278 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4284 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4285 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4291 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4292 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4298 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4299 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4305 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4306 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4312 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4313 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4319 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4320 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4326 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4327 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4333 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4334 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4340 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4341 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4347 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4348 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4354 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4355 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4364 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4365 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4371 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4372 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4378 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4379 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4385 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4386 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4392 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4393 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4399 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4400 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4406 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4407 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4413 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4414 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4420 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4421 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4427 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4428 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4434 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4435 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4441 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4442 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4448 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4449 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4455 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4456 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4462 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4463 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4570 …TX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is us…
4597 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the…
4758 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
5035 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5036 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5042 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5043 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5049 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5050 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5056 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5057 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5063 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5064 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5070 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5071 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5077 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5078 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5084 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5085 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5091 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5092 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5098 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5099 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5105 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5106 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5112 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5113 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5119 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5120 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5126 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5127 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5133 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5134 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5140 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5141 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5147 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5148 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5154 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5155 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5161 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5162 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5168 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5169 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5175 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5176 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5182 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5183 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5189 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5190 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5196 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5197 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5203 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5204 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5210 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5211 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5217 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5218 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5224 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5225 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5231 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5232 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5238 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5239 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5245 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5246 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5252 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5253 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5262 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5263 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5269 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5270 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5276 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5277 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5283 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5284 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5290 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5291 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5297 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
5298 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5304 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
5305 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5311 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
5312 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5318 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
5319 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5325 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
5326 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5332 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
5333 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5339 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
5340 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5346 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
5347 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5353 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
5354 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5360 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
5361 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5367 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
5368 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5374 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
5375 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5381 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
5382 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5388 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
5389 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5395 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
5396 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5402 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
5403 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5409 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
5410 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5416 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
5417 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5423 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
5424 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5430 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
5431 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5437 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
5438 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5444 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
5445 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5451 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
5452 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5458 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
5459 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5465 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
5466 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5472 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
5473 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5479 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
5480 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5484 /* Description: Read GPIO port */
5879 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
5880 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
5886 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
5887 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
5893 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
5894 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
5900 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
5901 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
5907 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
5908 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
5914 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
5915 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
5921 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
5922 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
5928 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
5929 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
5935 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
5936 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
5942 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
5943 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
5949 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
5950 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
5956 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
5957 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
5963 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
5964 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
5970 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
5971 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
5977 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
5978 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
5984 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
5985 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
5991 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
5992 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
5998 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
5999 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6005 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6006 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6012 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6013 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6019 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6020 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6026 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6027 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6033 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6034 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6040 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6041 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6047 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6048 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6054 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6055 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6061 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6062 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6068 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6069 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6075 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6076 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6082 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6083 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6089 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6090 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6096 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6097 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6106 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6107 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6113 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6114 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6120 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6121 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6127 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6128 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6134 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6135 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6141 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6142 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6148 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6149 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6155 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6156 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6162 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6163 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6169 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6170 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6176 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6177 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6183 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6184 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6190 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6191 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6197 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6198 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6204 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6205 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6211 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6212 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6218 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6219 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6225 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6226 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6232 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6233 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6239 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6240 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6246 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6247 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6253 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6254 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6260 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6261 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6267 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6268 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6274 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6275 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6281 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6282 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6288 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6289 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6295 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6296 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6302 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
6303 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6309 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
6310 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6316 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
6317 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6323 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
6324 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6603 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6604 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6610 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6611 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6617 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6618 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6627 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6628 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6634 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6635 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6641 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6642 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6749 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6750 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6756 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6757 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6763 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6764 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6773 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6774 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6780 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6781 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6787 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6788 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7257 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
7258 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7264 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
7265 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7271 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
7272 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7278 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
7279 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7285 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
7286 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7292 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
7293 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
7299 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
7300 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
7306 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
7307 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
7313 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
7314 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
7320 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
7321 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
7327 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
7328 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
7334 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
7335 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
7341 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
7342 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
7348 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
7349 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
7355 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
7356 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
7362 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
7363 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
7369 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
7370 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
7376 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
7377 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
7383 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
7384 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
7390 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
7391 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
7397 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
7398 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
7404 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
7405 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
7411 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
7412 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
7418 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
7419 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
7425 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
7426 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
7432 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
7433 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
7439 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
7440 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
7446 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
7447 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
7453 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
7454 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
7460 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
7461 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
7467 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
7468 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
7474 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
7475 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
7484 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
7485 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
7491 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
7492 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
7498 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
7499 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
7505 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
7506 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
7512 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
7513 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
7519 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
7520 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
7526 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
7527 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
7533 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
7534 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
7540 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
7541 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
7547 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
7548 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
7554 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
7555 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
7561 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
7562 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
7568 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
7569 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
7575 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
7576 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
7582 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
7583 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
7589 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
7590 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
7596 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
7597 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
7603 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
7604 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
7610 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
7611 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
7617 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
7618 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
7624 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
7625 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
7631 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
7632 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
7638 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
7639 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
7645 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
7646 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
7652 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
7653 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
7659 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
7660 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
7666 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
7667 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
7673 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
7674 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
7680 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
7681 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
7687 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
7688 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
7694 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
7695 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
7701 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
7702 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
8009 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8010 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8016 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8017 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8023 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8024 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8030 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8031 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8037 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8038 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8044 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8045 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8051 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8052 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8061 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8062 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8068 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8069 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8075 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8076 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8082 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8083 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8089 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8090 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8096 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8097 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8103 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8104 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8156 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
8270 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8271 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8277 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8278 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8284 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8285 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8291 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8292 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8298 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8299 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8308 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8309 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8315 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8316 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8322 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8323 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8329 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8330 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8336 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8337 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8402 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPL…
8543 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8544 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8550 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8551 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8557 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8558 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8564 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8565 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8571 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8572 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8578 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8579 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8585 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8586 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8592 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8593 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8599 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8600 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8606 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8607 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8613 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
8614 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
8623 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8624 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8630 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8631 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8637 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8638 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8644 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8645 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8651 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8652 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8658 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8659 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8665 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8666 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8672 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8673 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8679 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8680 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8686 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8687 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8693 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
8694 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
9004 …hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by th…
9156 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9157 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9166 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9167 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9196 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9197 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9203 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9204 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9210 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9211 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9217 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9218 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9224 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9225 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9231 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9232 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9241 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9242 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9248 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9249 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9255 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9256 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9262 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9263 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9269 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9270 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9276 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9277 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9325 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9326 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9332 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9333 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9339 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9340 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9346 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9347 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9353 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9354 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9360 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9361 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9370 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9371 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9377 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9378 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9384 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9385 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9391 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9392 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9398 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9399 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9405 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9406 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9575 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9576 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9582 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9583 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9589 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9590 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9596 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9597 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9603 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9604 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9610 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9611 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9617 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9618 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9624 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9625 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9631 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9632 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9638 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9639 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9645 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9646 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9652 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9653 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9659 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9660 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9666 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9667 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9673 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9674 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9680 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9681 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9687 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9688 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9694 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9695 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9701 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9702 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9708 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
9709 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
9715 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
9716 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
9722 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
9723 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
9732 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9733 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9739 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9740 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9746 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9747 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9753 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9754 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9760 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9761 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9767 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9768 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9774 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9775 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9781 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9782 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9788 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9789 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9795 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9796 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9802 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9803 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9809 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9810 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9816 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9817 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9823 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9824 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9830 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9831 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9837 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9838 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9844 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9845 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9851 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9852 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9858 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9859 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9865 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
9866 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
9872 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
9873 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9879 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
9880 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
10062 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read afte…
10076 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10077 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10086 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10087 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10191 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
10192 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
10198 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10199 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10205 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10206 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10212 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10213 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10219 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10220 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10229 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
10230 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
10236 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10237 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10243 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10244 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10250 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10251 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10257 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10258 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10405 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer.…
10407 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. …
10430 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10431 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10437 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10438 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10444 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10445 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10454 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10455 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10461 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10462 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10468 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10469 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10489 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
10490 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
10493 /* Bit 0 : TX buffer over-read detected, and prevented */
10496 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
10497 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
10632 /* Description: Over-read character */
10634 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
10648 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10649 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10658 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10659 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10873 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10874 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10880 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10881 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10887 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10888 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10894 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10895 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10901 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10902 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10908 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10909 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10918 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10919 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10925 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10926 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10932 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10933 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10939 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10940 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10946 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10947 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10953 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10954 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11017 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11018 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11024 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
11025 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
11031 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11032 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11038 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11039 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11045 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11046 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11052 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11053 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11062 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11063 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11069 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
11070 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
11076 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11077 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11083 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11084 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11090 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11091 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11097 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11098 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11107 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
11108 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
11114 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
11115 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
11121 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
11122 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
11269 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11270 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11276 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11277 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11283 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11284 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11290 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11291 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11297 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11298 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11304 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11305 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11311 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11312 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11321 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11322 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11328 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11329 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11335 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11336 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11342 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11343 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11349 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11350 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11356 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11357 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11363 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11364 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11507 /* Bit 14 : Shortcut between READ event and SUSPEND task */
11522 /* Bit 26 : Enable or disable interrupt for READ event */
11523 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
11524 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
11561 /* Bit 26 : Write '1' to Enable interrupt for READ event */
11562 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
11563 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
11564 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
11565 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
11571 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
11572 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
11578 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11579 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11585 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11586 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11592 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11593 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11599 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11600 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11606 /* Bit 26 : Write '1' to Disable interrupt for READ event */
11607 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
11608 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
11609 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
11610 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
11616 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
11617 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
11623 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11624 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11630 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11631 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11637 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11638 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11644 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11645 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11651 /* Bit 3 : TX buffer over-read detected, and prevented */
11776 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
11778 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
11807 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
11808 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
11814 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11815 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11821 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11822 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11828 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11829 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11835 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
11836 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
11842 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
11843 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
11852 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
11853 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
11859 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11860 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11866 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11867 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11873 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11874 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11880 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
11881 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
11887 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
11888 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
11897 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
11898 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
11903 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
11904 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
11909 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
11910 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
11915 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
11916 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
12107 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12108 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12114 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12115 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12121 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12122 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12128 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
12129 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
12135 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
12136 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
12142 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12143 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12149 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12150 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12156 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12157 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12163 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12164 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12170 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
12171 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
12177 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
12178 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
12187 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12188 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12194 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12195 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12201 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12202 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12208 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
12209 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
12215 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
12216 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
12222 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12223 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12229 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12230 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12236 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12237 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12243 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12244 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12250 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
12251 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
12257 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
12258 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
12267 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
12268 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
12273 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
12274 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
12279 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
12280 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
12285 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
12286 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
12497 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12498 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12507 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12508 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */