Lines Matching full:disable

66 /* Description: Disable interrupt */
68 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
73 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
75 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
80 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
82 /* Bit 0 : Write '1' to Disable interrupt for END event */
87 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
99 /* Bits 1..0 : Enable or disable AAR */
102 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
528 /* Description: Disable protection mechanism in debug interface mode */
530 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This reg…
534 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
936 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
964 /* Description: Disable interrupt */
966 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
971 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
973 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
978 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
980 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
985 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
999 /* Bits 1..0 : Enable or disable CCM */
1002 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1090 /* Description: Disable interrupt */
1092 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
1097 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
1099 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
1104 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
1106 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
1111 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
1113 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
1118 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
1182 /* Bit 17 : Enable or disable external source for LFCLK */
1185 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
1188 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
1191 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external sour…
1236 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
1242 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
1248 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
1254 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
1260 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
1264 /* Description: Enable or disable interrupt */
1266 /* Bit 3 : Enable or disable interrupt for CROSS event */
1269 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
1272 /* Bit 2 : Enable or disable interrupt for UP event */
1275 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1278 /* Bit 1 : Enable or disable interrupt for DOWN event */
1281 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1284 /* Bit 0 : Enable or disable interrupt for READY event */
1287 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1322 /* Description: Disable interrupt */
1324 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
1329 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1331 /* Bit 2 : Write '1' to Disable interrupt for UP event */
1336 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1338 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
1343 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1345 /* Bit 0 : Write '1' to Disable interrupt for READY event */
1350 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1364 /* Bits 1..0 : Enable or disable COMP */
1367 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1481 /* Description: Disable interrupt */
1483 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
1488 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1490 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
1495 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1509 /* Description: Enable or disable interrupt */
1511 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1514 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1517 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1520 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1523 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1526 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1529 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1532 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1535 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1538 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1541 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1544 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1547 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1550 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1553 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1556 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1559 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1562 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1565 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1568 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1571 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1574 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1577 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1580 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1583 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1586 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1589 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1592 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1595 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1598 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1601 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1604 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1723 /* Description: Disable interrupt */
1725 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
1730 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1732 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
1737 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1739 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
1744 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1746 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
1751 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1753 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
1758 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1760 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
1765 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1767 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
1772 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1774 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
1779 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1781 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
1786 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1788 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
1793 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1795 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
1800 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1802 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
1807 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1809 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
1814 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1816 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
1821 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1823 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
1828 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1830 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
1835 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
2215 /* Description: Disable interrupt */
2217 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
2222 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2224 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
2229 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2231 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
2236 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2238 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
2243 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2245 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
2250 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2252 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
2257 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2259 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
2264 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2266 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
2271 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2273 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
2278 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2313 /* Description: Enable or disable interrupt */
2315 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
2318 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2321 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2324 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2327 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2330 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2358 /* Description: Disable interrupt */
2360 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
2365 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2367 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
2372 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2374 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
2379 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2387 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2601 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
2607 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
2613 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
2619 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
2625 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
2660 /* Description: Disable interrupt */
2662 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
2667 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2669 /* Bit 2 : Write '1' to Disable interrupt for UP event */
2674 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2676 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
2681 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2683 /* Bit 0 : Write '1' to Disable interrupt for READY event */
2688 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2702 /* Bits 1..0 : Enable or disable LPCOMP */
2705 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2779 /* Description: Enable or disable interrupt */
2781 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2784 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2787 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2790 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2793 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
2796 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2799 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
2802 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2805 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
2808 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
2811 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
2814 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
2817 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2820 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
2823 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2826 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
2829 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2832 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
2835 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2838 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
2841 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2844 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
2847 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
2850 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
2941 /* Description: Disable interrupt */
2943 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
2948 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2950 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
2955 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2957 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
2962 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2964 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
2969 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2971 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
2976 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2978 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
2983 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
2985 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
2990 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
2992 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
2997 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
2999 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
3004 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3006 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
3011 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3013 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
3018 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3020 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
3025 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3028 /* Description: Enable or disable non-maskable interrupt */
3030 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
3033 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
3036 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
3039 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
3042 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
3045 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
3048 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
3051 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
3054 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
3057 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
3060 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
3063 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
3066 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
3069 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
3072 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
3075 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
3078 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
3081 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
3084 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
3087 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
3090 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
3093 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
3096 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
3099 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
3190 /* Description: Disable non-maskable interrupt */
3192 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
3197 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3199 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
3204 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3206 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
3211 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3213 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
3218 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3220 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
3225 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3227 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
3232 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3234 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
3239 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3241 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
3246 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3248 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
3253 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3255 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
3260 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3262 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
3267 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3269 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
3274 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3667 /* Description: Enable/disable regions watch */
3669 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3672 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3675 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3678 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3681 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3684 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3687 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3690 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3693 /* Bit 7 : Enable/disable read access watch in region[3] */
3696 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3699 /* Bit 6 : Enable/disable write access watch in region[3] */
3702 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3705 /* Bit 5 : Enable/disable read access watch in region[2] */
3708 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3711 /* Bit 4 : Enable/disable write access watch in region[2] */
3714 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3717 /* Bit 3 : Enable/disable read access watch in region[1] */
3720 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3723 /* Bit 2 : Enable/disable write access watch in region[1] */
3726 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3729 /* Bit 1 : Enable/disable read access watch in region[0] */
3732 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3735 /* Bit 0 : Enable/disable write access watch in region[0] */
3738 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3829 /* Description: Disable regions watch */
3831 /* Bit 27 : Disable read access watch in PREGION[1] */
3836 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3838 /* Bit 26 : Disable write access watch in PREGION[1] */
3843 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3845 /* Bit 25 : Disable read access watch in PREGION[0] */
3850 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3852 /* Bit 24 : Disable write access watch in PREGION[0] */
3857 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3859 /* Bit 7 : Disable read access watch in region[3] */
3864 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3866 /* Bit 6 : Disable write access watch in region[3] */
3871 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3873 /* Bit 5 : Disable read access watch in region[2] */
3878 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3880 /* Bit 4 : Disable write access watch in region[2] */
3885 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3887 /* Bit 3 : Disable read access watch in region[1] */
3892 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3894 /* Bit 2 : Disable write access watch in region[1] */
3899 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3901 /* Bit 1 : Disable read access watch in region[0] */
3906 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3908 /* Bit 0 : Disable write access watch in region[0] */
3913 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
4148 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4154 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4158 /* Description: Enable or disable interrupt */
4160 /* Bit 20 : Enable or disable interrupt for STARTED event */
4163 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4166 /* Bit 19 : Enable or disable interrupt for SELECTED event */
4169 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4172 /* Bit 18 : Enable or disable interrupt for COLLISION event */
4175 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4178 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
4181 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4184 /* Bit 12 : Enable or disable interrupt for ENDTX event */
4187 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4190 /* Bit 11 : Enable or disable interrupt for ENDRX event */
4193 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4196 /* Bit 10 : Enable or disable interrupt for RXERROR event */
4199 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4202 /* Bit 7 : Enable or disable interrupt for ERROR event */
4205 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4208 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
4211 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4214 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
4217 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4220 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
4223 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4226 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
4229 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4232 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4235 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4238 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4241 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4244 /* Bit 0 : Enable or disable interrupt for READY event */
4247 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4359 /* Description: Disable interrupt */
4361 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
4366 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4368 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
4373 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4375 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
4380 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4382 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
4387 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4389 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
4394 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4396 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
4401 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4403 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
4408 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4410 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
4415 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4417 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
4422 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4424 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
4429 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4431 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
4436 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4438 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
4443 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4445 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
4450 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4452 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
4457 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4459 /* Bit 0 : Write '1' to Disable interrupt for READY event */
4464 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4807 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
4813 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
6577 /* Description: Enable or disable interrupt */
6579 /* Bit 2 : Enable or disable interrupt for END event */
6582 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
6585 /* Bit 1 : Enable or disable interrupt for STOPPED event */
6588 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6591 /* Bit 0 : Enable or disable interrupt for STARTED event */
6594 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6622 /* Description: Disable interrupt */
6624 /* Bit 2 : Write '1' to Disable interrupt for END event */
6629 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6631 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
6636 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6638 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
6643 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6648 /* Bit 0 : Enable or disable PDM module */
6651 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
6768 /* Description: Disable interrupt */
6770 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
6775 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
6777 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
6782 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
6784 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
6789 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
6896 /* Bit 0 : Enable or disable power failure comparator */
6899 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
6973 /* Bit 0 : Enable or disable DC/DC converter */
6976 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
7059 /* Bit 31 : Enable or disable channel 31 */
7062 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7065 /* Bit 30 : Enable or disable channel 30 */
7068 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7071 /* Bit 29 : Enable or disable channel 29 */
7074 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7077 /* Bit 28 : Enable or disable channel 28 */
7080 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7083 /* Bit 27 : Enable or disable channel 27 */
7086 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7089 /* Bit 26 : Enable or disable channel 26 */
7092 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7095 /* Bit 25 : Enable or disable channel 25 */
7098 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7101 /* Bit 24 : Enable or disable channel 24 */
7104 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7107 /* Bit 23 : Enable or disable channel 23 */
7110 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7113 /* Bit 22 : Enable or disable channel 22 */
7116 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
7119 /* Bit 21 : Enable or disable channel 21 */
7122 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
7125 /* Bit 20 : Enable or disable channel 20 */
7128 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
7131 /* Bit 19 : Enable or disable channel 19 */
7134 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
7137 /* Bit 18 : Enable or disable channel 18 */
7140 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
7143 /* Bit 17 : Enable or disable channel 17 */
7146 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
7149 /* Bit 16 : Enable or disable channel 16 */
7152 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
7155 /* Bit 15 : Enable or disable channel 15 */
7158 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
7161 /* Bit 14 : Enable or disable channel 14 */
7164 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
7167 /* Bit 13 : Enable or disable channel 13 */
7170 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
7173 /* Bit 12 : Enable or disable channel 12 */
7176 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
7179 /* Bit 11 : Enable or disable channel 11 */
7182 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
7185 /* Bit 10 : Enable or disable channel 10 */
7188 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
7191 /* Bit 9 : Enable or disable channel 9 */
7194 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
7197 /* Bit 8 : Enable or disable channel 8 */
7200 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
7203 /* Bit 7 : Enable or disable channel 7 */
7206 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
7209 /* Bit 6 : Enable or disable channel 6 */
7212 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
7215 /* Bit 5 : Enable or disable channel 5 */
7218 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
7221 /* Bit 4 : Enable or disable channel 4 */
7224 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
7227 /* Bit 3 : Enable or disable channel 3 */
7230 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
7233 /* Bit 2 : Enable or disable channel 2 */
7236 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
7239 /* Bit 1 : Enable or disable channel 1 */
7242 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
7245 /* Bit 0 : Enable or disable channel 0 */
7248 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
7486 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
7493 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
7500 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
7507 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
7514 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
7521 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
7528 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
7535 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
7542 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
7549 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
7556 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
7563 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
7570 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
7577 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
7584 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
7591 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
7598 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
7605 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
7612 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
7619 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
7626 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
7633 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
7640 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
7647 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
7654 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
7661 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
7668 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
7675 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
7682 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
7689 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
7696 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
7703 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
7931 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
7937 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
7943 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
7949 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
7955 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
7959 /* Description: Enable or disable interrupt */
7961 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
7964 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
7967 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
7970 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
7973 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
7976 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
7979 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
7982 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
7985 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
7988 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
7991 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
7994 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
7997 /* Bit 1 : Enable or disable interrupt for STOPPED event */
8000 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8056 /* Description: Disable interrupt */
8058 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
8063 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
8065 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
8070 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
8072 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
8077 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
8079 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
8084 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
8086 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
8091 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
8093 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
8098 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
8100 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
8105 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8110 /* Bit 0 : Enable or disable PWM module */
8225 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
8231 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8237 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
8243 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8249 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
8255 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8261 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
8303 /* Description: Disable interrupt */
8305 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
8310 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8312 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
8317 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
8319 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
8324 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
8326 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
8331 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
8333 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
8338 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
8343 /* Bit 0 : Enable or disable the quadrature decoder */
8346 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
8492 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
8498 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
8504 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
8510 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
8516 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
8522 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
8525 /* Bit 1 : Shortcut between END event and DISABLE task */
8528 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
8534 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
8618 /* Description: Disable interrupt */
8620 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
8625 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
8627 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
8632 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
8634 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
8639 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
8641 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
8646 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
8648 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
8653 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
8655 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
8660 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
8662 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
8667 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
8669 /* Bit 3 : Write '1' to Disable interrupt for END event */
8674 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
8676 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
8681 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
8683 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
8688 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
8690 /* Bit 0 : Write '1' to Disable interrupt for READY event */
8695 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
8806 /* Bit 25 : Enable or disable packet whitening */
8809 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
8892 /* Bit 7 : Enable or disable reception on logical address 7. */
8895 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
8898 /* Bit 6 : Enable or disable reception on logical address 6. */
8901 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
8904 /* Bit 5 : Enable or disable reception on logical address 5. */
8907 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
8910 /* Bit 4 : Enable or disable reception on logical address 4. */
8913 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
8916 /* Bit 3 : Enable or disable reception on logical address 3. */
8919 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
8922 /* Bit 2 : Enable or disable reception on logical address 2. */
8925 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
8928 /* Bit 1 : Enable or disable reception on logical address 1. */
8931 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
8934 /* Bit 0 : Enable or disable reception on logical address 0. */
8937 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
9064 /* Bit 7 : Enable or disable device address matching using device address 7 */
9070 /* Bit 6 : Enable or disable device address matching using device address 6 */
9076 /* Bit 5 : Enable or disable device address matching using device address 5 */
9082 /* Bit 4 : Enable or disable device address matching using device address 4 */
9088 /* Bit 3 : Enable or disable device address matching using device address 3 */
9094 /* Bit 2 : Enable or disable device address matching using device address 2 */
9100 /* Bit 1 : Enable or disable device address matching using device address 1 */
9106 /* Bit 0 : Enable or disable device address matching using device address 0 */
9147 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9161 /* Description: Disable interrupt */
9163 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
9168 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
9236 /* Description: Disable interrupt */
9238 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
9243 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9245 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
9250 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9252 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
9257 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9259 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
9264 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9266 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
9271 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9273 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
9278 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
9281 /* Description: Enable or disable event routing */
9283 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
9286 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
9289 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
9292 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
9295 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
9298 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
9301 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
9304 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
9307 /* Bit 1 : Enable or disable event routing for OVRFLW event */
9310 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
9313 /* Bit 0 : Enable or disable event routing for TICK event */
9316 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
9365 /* Description: Disable event routing */
9367 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
9372 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9374 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
9379 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9381 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
9386 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9388 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
9393 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9395 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
9400 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9402 /* Bit 0 : Write '1' to Disable event routing for TICK event */
9407 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
9435 /* Description: Enable or disable interrupt */
9437 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
9440 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
9443 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
9446 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
9449 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
9452 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
9455 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
9458 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
9461 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
9464 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
9467 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
9470 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
9473 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
9476 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
9479 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
9482 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
9485 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
9488 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
9491 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
9494 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
9497 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
9500 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
9503 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
9506 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
9509 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
9512 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
9515 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
9518 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
9521 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
9524 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
9527 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
9530 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
9533 /* Bit 5 : Enable or disable interrupt for STOPPED event */
9536 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9539 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
9542 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
9545 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
9548 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
9551 /* Bit 2 : Enable or disable interrupt for DONE event */
9554 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
9557 /* Bit 1 : Enable or disable interrupt for END event */
9560 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
9563 /* Bit 0 : Enable or disable interrupt for STARTED event */
9566 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
9727 /* Description: Disable interrupt */
9729 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
9734 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
9736 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
9741 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
9743 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
9748 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
9750 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
9755 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
9757 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
9762 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
9764 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
9769 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
9771 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
9776 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
9778 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
9783 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
9785 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
9790 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
9792 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
9797 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
9799 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
9804 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
9806 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
9811 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
9813 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
9818 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
9820 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
9825 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
9827 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
9832 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
9834 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
9839 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
9841 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
9846 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9848 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
9853 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
9855 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
9860 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
9862 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
9867 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
9869 /* Bit 1 : Write '1' to Disable interrupt for END event */
9874 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
9876 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
9881 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
9893 /* Description: Enable or disable ADC */
9895 /* Bit 0 : Enable or disable ADC */
9898 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
10081 /* Description: Disable interrupt */
10083 /* Bit 2 : Write '1' to Disable interrupt for READY event */
10088 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
10093 /* Bits 3..0 : Enable or disable SPI */
10096 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
10182 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
10224 /* Description: Disable interrupt */
10226 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
10231 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
10233 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
10238 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10240 /* Bit 6 : Write '1' to Disable interrupt for END event */
10245 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
10247 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10252 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10254 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
10259 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
10264 /* Bits 3..0 : Enable or disable SPIM */
10267 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
10350 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10380 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10421 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
10449 /* Description: Disable interrupt */
10451 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
10456 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
10458 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10463 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10465 /* Bit 1 : Write '1' to Disable interrupt for END event */
10470 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
10503 /* Bits 3..0 : Enable or disable SPI slave */
10506 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
10653 /* Description: Disable interrupt */
10655 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
10660 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
10798 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
10804 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
10810 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
10816 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
10822 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
10828 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
10834 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10840 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10846 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10852 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10858 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10864 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10913 /* Description: Disable interrupt */
10915 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
10920 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
10922 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
10927 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
10929 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
10934 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
10936 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
10941 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
10943 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
10948 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
10950 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
10955 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11002 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
11008 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11057 /* Description: Disable interrupt */
11059 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11064 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11066 /* Bit 14 : Write '1' to Disable interrupt for BB event */
11071 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
11073 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11078 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11080 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
11085 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
11087 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
11092 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
11094 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11099 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11128 /* Bits 3..0 : Enable or disable TWI */
11131 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
11191 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
11197 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
11203 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
11209 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11215 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
11219 /* Description: Enable or disable interrupt */
11221 /* Bit 24 : Enable or disable interrupt for LASTTX event */
11224 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
11227 /* Bit 23 : Enable or disable interrupt for LASTRX event */
11230 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
11233 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11236 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11239 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11242 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11245 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
11248 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
11251 /* Bit 9 : Enable or disable interrupt for ERROR event */
11254 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11257 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11260 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11316 /* Description: Disable interrupt */
11318 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
11323 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
11325 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
11330 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
11332 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11337 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11339 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11344 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11346 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11351 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11353 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11358 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11360 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11365 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11391 /* Bits 3..0 : Enable or disable TWIM */
11394 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
11460 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11490 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11510 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11516 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11520 /* Description: Enable or disable interrupt */
11522 /* Bit 26 : Enable or disable interrupt for READ event */
11525 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
11528 /* Bit 25 : Enable or disable interrupt for WRITE event */
11531 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
11534 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11537 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11540 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11543 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11546 /* Bit 9 : Enable or disable interrupt for ERROR event */
11549 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11552 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11555 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11604 /* Description: Disable interrupt */
11606 /* Bit 26 : Write '1' to Disable interrupt for READ event */
11611 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
11613 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
11618 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
11620 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11625 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11627 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11632 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11634 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11639 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11641 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11646 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11679 /* Bits 3..0 : Enable or disable TWIS */
11682 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
11763 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
11769 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
11792 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
11798 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
11847 /* Description: Disable interrupt */
11849 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
11854 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
11856 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11861 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11863 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
11868 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
11870 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
11875 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
11877 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
11882 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
11884 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
11889 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
11921 /* Bits 3..0 : Enable or disable UART */
11924 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
12023 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
12029 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
12033 /* Description: Enable or disable interrupt */
12035 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
12038 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
12041 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
12044 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
12047 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
12050 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
12053 /* Bit 17 : Enable or disable interrupt for RXTO event */
12056 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
12059 /* Bit 9 : Enable or disable interrupt for ERROR event */
12062 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
12065 /* Bit 8 : Enable or disable interrupt for ENDTX event */
12068 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
12071 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
12074 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
12077 /* Bit 4 : Enable or disable interrupt for ENDRX event */
12080 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
12083 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
12086 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
12089 /* Bit 1 : Enable or disable interrupt for NCTS event */
12092 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
12095 /* Bit 0 : Enable or disable interrupt for CTS event */
12098 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
12182 /* Description: Disable interrupt */
12184 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
12189 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
12191 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
12196 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
12198 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
12203 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
12205 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
12210 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
12212 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
12217 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
12219 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
12224 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12226 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
12231 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
12233 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
12238 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12240 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
12245 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
12247 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
12252 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
12254 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
12259 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
12291 /* Bits 3..0 : Enable or disable UARTE */
12294 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
12472 /* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to…
12476 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
12502 /* Description: Disable interrupt */
12504 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
12509 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
12581 /* Bit 7 : Enable or disable RR[7] register */
12584 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
12587 /* Bit 6 : Enable or disable RR[6] register */
12590 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
12593 /* Bit 5 : Enable or disable RR[5] register */
12596 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
12599 /* Bit 4 : Enable or disable RR[4] register */
12602 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
12605 /* Bit 3 : Enable or disable RR[3] register */
12608 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
12611 /* Bit 2 : Enable or disable RR[2] register */
12614 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
12617 /* Bit 1 : Enable or disable RR[1] register */
12620 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
12623 /* Bit 0 : Enable or disable RR[0] register */
12626 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */