Lines Matching full:enable

42 /* Description: Enable interrupt */
44 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
49 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
51 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
56 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
58 /* Bit 0 : Write '1' to Enable interrupt for END event */
63 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
97 /* Description: Enable AAR */
99 /* Bits 1..0 : Enable or disable AAR */
100 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
101 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
103 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
140 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
144 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
146 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
150 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
152 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
156 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
158 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
162 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
164 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
168 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
170 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
174 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
176 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
180 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
182 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
186 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
188 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
192 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
194 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
198 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
200 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
204 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
206 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
210 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
212 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
216 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
218 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
222 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
224 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
228 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
230 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
234 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
236 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
240 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
242 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
246 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
248 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
252 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
254 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
258 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
260 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
264 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
266 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
270 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
272 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
276 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
278 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
282 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
284 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
288 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
290 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
294 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
296 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
300 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
302 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
306 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
308 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
312 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
314 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
318 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
320 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
324 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
326 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
330 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
335 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
341 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
347 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
353 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
359 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
365 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
371 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
377 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
383 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
389 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
395 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
401 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
407 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
413 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
419 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
425 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
431 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
437 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
443 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
449 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
455 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
461 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
467 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
473 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
479 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
485 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
491 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
497 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
503 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
509 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
515 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
521 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
533 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
539 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
545 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
551 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
557 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
563 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
569 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
575 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
581 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
587 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
593 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
599 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
605 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
611 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
617 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
623 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
629 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
635 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
641 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
647 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
653 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
659 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
665 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
671 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
677 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
683 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
689 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
695 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
701 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
707 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
713 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
719 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
725 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
734 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
740 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
746 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
752 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
758 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
764 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
770 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
776 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
782 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
788 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
794 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
800 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
806 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
812 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
818 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
824 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
830 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
836 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
842 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
848 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
854 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
860 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
866 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
872 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
878 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
884 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
890 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
896 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
902 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
908 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
914 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
920 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
937 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
940 /* Description: Enable interrupt */
942 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
947 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
949 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
954 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
956 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
961 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
997 /* Description: Enable */
999 /* Bits 1..0 : Enable or disable CCM */
1000 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1001 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1003 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1059 /* Description: Enable interrupt */
1061 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
1066 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
1068 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
1073 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
1075 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
1080 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
1082 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
1087 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
1182 /* Bit 17 : Enable or disable external source for LFCLK */
1186 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (S…
1188 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
1192 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
1237 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1243 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1249 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1255 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1261 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1264 /* Description: Enable or disable interrupt */
1266 /* Bit 3 : Enable or disable interrupt for CROSS event */
1270 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1272 /* Bit 2 : Enable or disable interrupt for UP event */
1276 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1278 /* Bit 1 : Enable or disable interrupt for DOWN event */
1282 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1284 /* Bit 0 : Enable or disable interrupt for READY event */
1288 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1291 /* Description: Enable interrupt */
1293 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
1298 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1300 /* Bit 2 : Write '1' to Enable interrupt for UP event */
1305 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1307 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
1312 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1314 /* Bit 0 : Write '1' to Enable interrupt for READY event */
1319 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1362 /* Description: COMP enable */
1364 /* Bits 1..0 : Enable or disable COMP */
1365 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1366 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1368 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1440 /* Description: Comparator hysteresis enable */
1464 /* Description: Enable interrupt */
1466 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
1471 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1473 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
1478 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1509 /* Description: Enable or disable interrupt */
1511 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1515 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1517 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1521 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1523 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1527 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1529 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1533 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1535 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1539 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1541 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1545 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1547 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1551 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1553 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1557 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1559 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1563 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1565 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1569 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1571 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1575 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1577 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1581 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1583 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1587 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1589 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1593 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1595 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1599 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1601 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1605 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1608 /* Description: Enable interrupt */
1610 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
1615 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1617 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
1622 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1624 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
1629 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1631 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
1636 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1638 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
1643 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1645 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
1650 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1652 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
1657 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1659 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
1664 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1666 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
1671 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1673 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
1678 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1680 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
1685 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1687 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
1692 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1694 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
1699 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1701 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
1706 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1708 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
1713 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1715 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
1720 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
2149 /* Description: Enable interrupt */
2151 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
2156 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
2158 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
2163 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
2165 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
2170 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
2172 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
2177 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
2179 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
2184 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
2186 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
2191 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
2193 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
2198 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
2200 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
2205 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2207 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
2212 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2313 /* Description: Enable or disable interrupt */
2315 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
2319 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2321 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2325 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2327 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2331 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2334 /* Description: Enable interrupt */
2336 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
2341 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2343 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
2348 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2350 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
2355 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2382 /* Description: Enable I2S module. */
2384 /* Bit 0 : Enable I2S module. */
2385 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2386 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2388 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2400 /* Description: Reception (RX) enable. */
2402 /* Bit 0 : Reception (RX) enable. */
2409 /* Description: Transmission (TX) enable. */
2411 /* Bit 0 : Transmission (TX) enable. */
2418 /* Description: Master clock generator enable. */
2420 /* Bit 0 : Master clock generator enable. */
2496 /* Description: Enable channels. */
2498 /* Bits 1..0 : Enable channels. */
2602 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2608 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2614 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2620 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2626 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2629 /* Description: Enable interrupt */
2631 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
2636 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2638 /* Bit 2 : Write '1' to Enable interrupt for UP event */
2643 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2645 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
2650 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2652 /* Bit 0 : Write '1' to Enable interrupt for READY event */
2657 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2700 /* Description: Enable LPCOMP */
2702 /* Bits 1..0 : Enable or disable LPCOMP */
2703 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2704 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.…
2706 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2766 /* Description: Comparator hysteresis enable */
2768 /* Bit 0 : Comparator hysteresis enable */
2779 /* Description: Enable or disable interrupt */
2781 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2785 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2787 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2791 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2793 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
2797 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2799 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
2803 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2805 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
2809 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2811 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
2815 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2817 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2821 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2823 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2827 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2829 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2833 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2835 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2839 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2841 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2845 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2847 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
2851 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2854 /* Description: Enable interrupt */
2856 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
2861 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2863 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
2868 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2870 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
2875 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2877 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
2882 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2884 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
2889 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2891 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
2896 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2898 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
2903 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2905 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
2910 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2912 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
2917 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2919 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
2924 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2926 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
2931 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2933 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
2938 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
3028 /* Description: Enable or disable non-maskable interrupt */
3030 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
3034 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3036 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
3040 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3042 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
3046 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3048 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
3052 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3054 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
3058 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
3060 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
3064 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
3066 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
3070 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
3072 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
3076 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
3078 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
3082 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
3084 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
3088 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
3090 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
3094 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
3096 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
3100 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
3103 /* Description: Enable non-maskable interrupt */
3105 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
3110 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
3112 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
3117 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3119 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
3124 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3126 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
3131 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3133 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
3138 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3140 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
3145 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3147 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
3152 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3154 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
3159 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3161 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
3166 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3168 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
3173 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3175 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
3180 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3182 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
3187 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3667 /* Description: Enable/disable regions watch */
3669 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3673 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3675 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3679 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3681 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3685 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3687 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3691 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3693 /* Bit 7 : Enable/disable read access watch in region[3] */
3697 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3699 /* Bit 6 : Enable/disable write access watch in region[3] */
3703 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3705 /* Bit 5 : Enable/disable read access watch in region[2] */
3709 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3711 /* Bit 4 : Enable/disable write access watch in region[2] */
3715 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3717 /* Bit 3 : Enable/disable read access watch in region[1] */
3721 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3723 /* Bit 2 : Enable/disable write access watch in region[1] */
3727 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3729 /* Bit 1 : Enable/disable read access watch in region[0] */
3733 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3735 /* Bit 0 : Enable/disable write access watch in region[0] */
3739 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3742 /* Description: Enable regions watch */
3744 /* Bit 27 : Enable read access watch in PREGION[1] */
3749 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3751 /* Bit 26 : Enable write access watch in PREGION[1] */
3756 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3758 /* Bit 25 : Enable read access watch in PREGION[0] */
3763 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3765 /* Bit 24 : Enable write access watch in PREGION[0] */
3770 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3772 /* Bit 7 : Enable read access watch in region[3] */
3777 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3779 /* Bit 6 : Enable write access watch in region[3] */
3784 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3786 /* Bit 5 : Enable read access watch in region[2] */
3791 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3793 /* Bit 4 : Enable write access watch in region[2] */
3798 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3800 /* Bit 3 : Enable read access watch in region[1] */
3805 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3807 /* Bit 2 : Enable write access watch in region[1] */
3812 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3814 /* Bit 1 : Enable read access watch in region[0] */
3819 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3821 /* Bit 0 : Enable write access watch in region[0] */
3826 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
4149 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4155 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4158 /* Description: Enable or disable interrupt */
4160 /* Bit 20 : Enable or disable interrupt for STARTED event */
4164 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4166 /* Bit 19 : Enable or disable interrupt for SELECTED event */
4170 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4172 /* Bit 18 : Enable or disable interrupt for COLLISION event */
4176 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4178 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
4182 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4184 /* Bit 12 : Enable or disable interrupt for ENDTX event */
4188 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4190 /* Bit 11 : Enable or disable interrupt for ENDRX event */
4194 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4196 /* Bit 10 : Enable or disable interrupt for RXERROR event */
4200 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4202 /* Bit 7 : Enable or disable interrupt for ERROR event */
4206 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4208 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
4212 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4214 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
4218 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4220 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
4224 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4226 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
4230 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4232 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4236 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4238 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4242 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4244 /* Bit 0 : Enable or disable interrupt for READY event */
4248 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4251 /* Description: Enable interrupt */
4253 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
4258 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4260 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
4265 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4267 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
4272 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4274 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
4279 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4281 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
4286 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4288 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
4293 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4295 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
4300 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4302 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
4307 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4309 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
4314 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4316 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
4321 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4323 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
4328 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4330 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
4335 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4337 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
4342 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4344 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
4349 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4351 /* Bit 0 : Write '1' to Enable interrupt for READY event */
4356 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4804 /* Bit 8 : Cache profiling enable */
4808 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4810 /* Bit 0 : Cache enable */
4814 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
6577 /* Description: Enable or disable interrupt */
6579 /* Bit 2 : Enable or disable interrupt for END event */
6583 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6585 /* Bit 1 : Enable or disable interrupt for STOPPED event */
6589 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6591 /* Bit 0 : Enable or disable interrupt for STARTED event */
6595 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6598 /* Description: Enable interrupt */
6600 /* Bit 2 : Write '1' to Enable interrupt for END event */
6605 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6607 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
6612 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6614 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
6619 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6646 /* Description: PDM module enable register */
6648 /* Bit 0 : Enable or disable PDM module */
6649 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6650 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6652 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6744 /* Description: Enable interrupt */
6746 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
6751 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
6753 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
6758 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
6760 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
6765 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
6872 /* Bit 0 : Enable System OFF mode */
6875 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
6896 /* Bit 0 : Enable or disable power failure comparator */
6900 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
6971 /* Description: DC/DC enable register */
6973 /* Bit 0 : Enable or disable DC/DC converter */
6977 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
7057 /* Description: Channel enable register */
7059 /* Bit 31 : Enable or disable channel 31 */
7063 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7065 /* Bit 30 : Enable or disable channel 30 */
7069 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7071 /* Bit 29 : Enable or disable channel 29 */
7075 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7077 /* Bit 28 : Enable or disable channel 28 */
7081 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7083 /* Bit 27 : Enable or disable channel 27 */
7087 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7089 /* Bit 26 : Enable or disable channel 26 */
7093 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7095 /* Bit 25 : Enable or disable channel 25 */
7099 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7101 /* Bit 24 : Enable or disable channel 24 */
7105 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7107 /* Bit 23 : Enable or disable channel 23 */
7111 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7113 /* Bit 22 : Enable or disable channel 22 */
7117 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7119 /* Bit 21 : Enable or disable channel 21 */
7123 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7125 /* Bit 20 : Enable or disable channel 20 */
7129 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7131 /* Bit 19 : Enable or disable channel 19 */
7135 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7137 /* Bit 18 : Enable or disable channel 18 */
7141 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7143 /* Bit 17 : Enable or disable channel 17 */
7147 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7149 /* Bit 16 : Enable or disable channel 16 */
7153 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7155 /* Bit 15 : Enable or disable channel 15 */
7159 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7161 /* Bit 14 : Enable or disable channel 14 */
7165 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7167 /* Bit 13 : Enable or disable channel 13 */
7171 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7173 /* Bit 12 : Enable or disable channel 12 */
7177 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7179 /* Bit 11 : Enable or disable channel 11 */
7183 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7185 /* Bit 10 : Enable or disable channel 10 */
7189 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7191 /* Bit 9 : Enable or disable channel 9 */
7195 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
7197 /* Bit 8 : Enable or disable channel 8 */
7201 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
7203 /* Bit 7 : Enable or disable channel 7 */
7207 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
7209 /* Bit 6 : Enable or disable channel 6 */
7213 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
7215 /* Bit 5 : Enable or disable channel 5 */
7219 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
7221 /* Bit 4 : Enable or disable channel 4 */
7225 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
7227 /* Bit 3 : Enable or disable channel 3 */
7231 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
7233 /* Bit 2 : Enable or disable channel 2 */
7237 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
7239 /* Bit 1 : Enable or disable channel 1 */
7243 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
7245 /* Bit 0 : Enable or disable channel 0 */
7249 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
7252 /* Description: Channel enable set register */
7254 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
7259 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7261 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
7266 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7268 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
7273 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7275 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
7280 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7282 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
7287 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
7289 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
7294 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
7296 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
7301 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
7303 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
7308 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
7310 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
7315 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
7317 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
7322 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
7324 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
7329 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
7331 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
7336 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
7338 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
7343 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
7345 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
7350 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
7352 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
7357 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
7359 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
7364 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
7366 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
7371 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
7373 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
7378 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
7380 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
7385 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
7387 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
7392 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
7394 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
7399 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
7401 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
7406 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
7408 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
7413 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
7415 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
7420 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
7422 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
7427 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
7429 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
7434 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
7436 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
7441 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
7443 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
7448 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
7450 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
7455 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
7457 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
7462 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
7464 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
7469 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
7471 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
7476 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
7479 /* Description: Channel enable clear register */
7481 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
7488 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
7495 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
7502 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
7509 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
7516 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
7523 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
7530 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
7537 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
7544 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
7551 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
7558 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
7565 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
7572 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
7579 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
7586 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
7593 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
7600 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
7607 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
7614 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
7621 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
7628 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
7635 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
7642 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
7649 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
7656 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
7663 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
7670 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
7677 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
7684 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
7691 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
7698 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
7932 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
7938 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
7944 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
7950 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
7956 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
7959 /* Description: Enable or disable interrupt */
7961 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
7965 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
7967 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
7971 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
7973 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
7977 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
7979 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
7983 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
7985 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
7989 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
7991 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
7995 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
7997 /* Bit 1 : Enable or disable interrupt for STOPPED event */
8001 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8004 /* Description: Enable interrupt */
8006 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
8011 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8013 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
8018 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8020 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
8025 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8027 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
8032 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8034 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
8039 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8041 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
8046 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
8048 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
8053 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8108 /* Description: PWM module enable register */
8110 /* Bit 0 : Enable or disable PWM module */
8111 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8112 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8114 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8226 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8232 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8238 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
8244 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8250 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
8256 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8262 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8265 /* Description: Enable interrupt */
8267 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
8272 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8274 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
8279 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
8281 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
8286 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
8288 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
8293 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
8295 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
8300 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
8341 /* Description: Enable the quadrature decoder */
8343 /* Bit 0 : Enable or disable the quadrature decoder */
8344 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8345 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8347 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8453 /* Description: Enable input debounce filters */
8455 /* Bit 0 : Enable input debounce filters */
8493 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
8499 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
8505 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
8511 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
8517 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
8523 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
8529 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
8535 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
8538 /* Description: Enable interrupt */
8540 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
8545 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
8547 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
8552 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
8554 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
8559 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
8561 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
8566 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
8568 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
8573 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
8575 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
8580 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
8582 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
8587 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
8589 /* Bit 3 : Write '1' to Enable interrupt for END event */
8594 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
8596 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
8601 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
8603 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
8608 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
8610 /* Bit 0 : Write '1' to Enable interrupt for READY event */
8615 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
8806 /* Bit 25 : Enable or disable packet whitening */
8810 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
8892 /* Bit 7 : Enable or disable reception on logical address 7. */
8896 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
8898 /* Bit 6 : Enable or disable reception on logical address 6. */
8902 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
8904 /* Bit 5 : Enable or disable reception on logical address 5. */
8908 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
8910 /* Bit 4 : Enable or disable reception on logical address 4. */
8914 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
8916 /* Bit 3 : Enable or disable reception on logical address 3. */
8920 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
8922 /* Bit 2 : Enable or disable reception on logical address 2. */
8926 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
8928 /* Bit 1 : Enable or disable reception on logical address 1. */
8932 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
8934 /* Bit 0 : Enable or disable reception on logical address 0. */
8938 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
9064 /* Bit 7 : Enable or disable device address matching using device address 7 */
9070 /* Bit 6 : Enable or disable device address matching using device address 6 */
9076 /* Bit 5 : Enable or disable device address matching using device address 5 */
9082 /* Bit 4 : Enable or disable device address matching using device address 4 */
9088 /* Bit 3 : Enable or disable device address matching using device address 3 */
9094 /* Bit 2 : Enable or disable device address matching using device address 2 */
9100 /* Bit 1 : Enable or disable device address matching using device address 1 */
9106 /* Bit 0 : Enable or disable device address matching using device address 0 */
9148 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9151 /* Description: Enable interrupt */
9153 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
9158 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
9191 /* Description: Enable interrupt */
9193 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
9198 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
9200 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
9205 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
9207 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
9212 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
9214 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
9219 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
9221 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
9226 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
9228 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
9233 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
9281 /* Description: Enable or disable event routing */
9283 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
9287 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
9289 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
9293 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
9295 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
9299 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
9301 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
9305 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
9307 /* Bit 1 : Enable or disable event routing for OVRFLW event */
9311 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
9313 /* Bit 0 : Enable or disable event routing for TICK event */
9317 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
9320 /* Description: Enable event routing */
9322 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
9327 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
9329 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
9334 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
9336 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
9341 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
9343 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
9348 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
9350 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
9355 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
9357 /* Bit 0 : Write '1' to Enable event routing for TICK event */
9362 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
9435 /* Description: Enable or disable interrupt */
9437 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
9441 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
9443 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
9447 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
9449 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
9453 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
9455 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
9459 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
9461 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
9465 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
9467 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
9471 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
9473 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
9477 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
9479 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
9483 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
9485 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
9489 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
9491 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
9495 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
9497 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
9501 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
9503 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
9507 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
9509 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
9513 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
9515 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
9519 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
9521 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
9525 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
9527 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
9531 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
9533 /* Bit 5 : Enable or disable interrupt for STOPPED event */
9537 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9539 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
9543 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
9545 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
9549 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
9551 /* Bit 2 : Enable or disable interrupt for DONE event */
9555 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
9557 /* Bit 1 : Enable or disable interrupt for END event */
9561 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
9563 /* Bit 0 : Enable or disable interrupt for STARTED event */
9567 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
9570 /* Description: Enable interrupt */
9572 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
9577 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
9579 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
9584 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
9586 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
9591 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
9593 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
9598 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
9600 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
9605 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
9607 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
9612 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
9614 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
9619 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
9621 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
9626 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
9628 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
9633 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
9635 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
9640 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
9642 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
9647 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
9649 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
9654 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
9656 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
9661 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
9663 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
9668 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
9670 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
9675 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
9677 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
9682 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
9684 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
9689 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9691 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
9696 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
9698 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
9703 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
9705 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
9710 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
9712 /* Bit 1 : Write '1' to Enable interrupt for END event */
9717 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
9719 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
9724 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
9893 /* Description: Enable or disable ADC */
9895 /* Bit 0 : Enable or disable ADC */
9896 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9897 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9899 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
9938 /* Bit 24 : Enable burst mode */
9944 /* Bit 20 : Enable differential mode */
10071 /* Description: Enable interrupt */
10073 /* Bit 2 : Write '1' to Enable interrupt for READY event */
10078 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
10091 /* Description: Enable SPI */
10093 /* Bits 3..0 : Enable or disable SPI */
10094 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10095 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10097 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
10183 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
10186 /* Description: Enable interrupt */
10188 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
10193 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
10195 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
10200 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10202 /* Bit 6 : Write '1' to Enable interrupt for END event */
10207 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
10209 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10214 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10216 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
10221 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
10262 /* Description: Enable SPIM */
10264 /* Bits 3..0 : Enable or disable SPIM */
10265 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10266 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10268 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
10422 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
10425 /* Description: Enable interrupt */
10427 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
10432 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
10434 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10439 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10441 /* Bit 1 : Write '1' to Enable interrupt for END event */
10446 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
10501 /* Description: Enable SPI slave */
10503 /* Bits 3..0 : Enable or disable SPI slave */
10504 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10505 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10507 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
10643 /* Description: Enable interrupt */
10645 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
10650 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
10799 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
10805 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
10811 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
10817 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
10823 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
10829 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
10835 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10841 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10847 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10853 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10859 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10865 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10868 /* Description: Enable interrupt */
10870 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
10875 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
10877 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
10882 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
10884 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
10889 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
10891 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
10896 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
10898 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
10903 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
10905 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
10910 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
11003 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
11009 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11012 /* Description: Enable interrupt */
11014 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11019 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11021 /* Bit 14 : Write '1' to Enable interrupt for BB event */
11026 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
11028 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11033 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
11035 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
11040 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
11042 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
11047 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
11049 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11054 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11126 /* Description: Enable TWI */
11128 /* Bits 3..0 : Enable or disable TWI */
11129 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11130 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11132 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
11192 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
11198 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
11204 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
11210 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11216 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11219 /* Description: Enable or disable interrupt */
11221 /* Bit 24 : Enable or disable interrupt for LASTTX event */
11225 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
11227 /* Bit 23 : Enable or disable interrupt for LASTRX event */
11231 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
11233 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11237 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11239 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11243 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11245 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
11249 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
11251 /* Bit 9 : Enable or disable interrupt for ERROR event */
11255 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11257 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11261 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11264 /* Description: Enable interrupt */
11266 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
11271 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
11273 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
11278 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
11280 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11285 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11287 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11292 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11294 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11299 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11301 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11306 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
11308 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11313 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11389 /* Description: Enable TWIM */
11391 /* Bits 3..0 : Enable or disable TWIM */
11392 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11393 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11395 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
11511 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11517 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11520 /* Description: Enable or disable interrupt */
11522 /* Bit 26 : Enable or disable interrupt for READ event */
11526 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
11528 /* Bit 25 : Enable or disable interrupt for WRITE event */
11532 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
11534 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11538 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11540 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11544 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11546 /* Bit 9 : Enable or disable interrupt for ERROR event */
11550 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11552 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11556 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11559 /* Description: Enable interrupt */
11561 /* Bit 26 : Write '1' to Enable interrupt for READ event */
11566 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
11568 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
11573 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
11575 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11580 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11582 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11587 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11589 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11594 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
11596 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11601 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11677 /* Description: Enable TWIS */
11679 /* Bits 3..0 : Enable or disable TWIS */
11680 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11681 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11683 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
11763 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
11769 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
11793 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
11799 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11802 /* Description: Enable interrupt */
11804 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
11809 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
11811 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11816 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
11818 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
11823 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
11825 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
11830 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
11832 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
11837 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
11839 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
11844 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
11919 /* Description: Enable UART */
11921 /* Bits 3..0 : Enable or disable UART */
11922 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11923 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11925 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
12024 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
12030 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
12033 /* Description: Enable or disable interrupt */
12035 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
12039 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
12041 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
12045 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
12047 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
12051 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
12053 /* Bit 17 : Enable or disable interrupt for RXTO event */
12057 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
12059 /* Bit 9 : Enable or disable interrupt for ERROR event */
12063 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
12065 /* Bit 8 : Enable or disable interrupt for ENDTX event */
12069 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
12071 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
12075 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
12077 /* Bit 4 : Enable or disable interrupt for ENDRX event */
12081 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
12083 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
12087 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
12089 /* Bit 1 : Enable or disable interrupt for NCTS event */
12093 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
12095 /* Bit 0 : Enable or disable interrupt for CTS event */
12099 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
12102 /* Description: Enable interrupt */
12104 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
12109 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
12111 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
12116 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
12118 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
12123 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
12125 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
12130 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
12132 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
12137 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
12139 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
12144 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12146 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
12151 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
12153 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
12158 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12160 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
12165 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
12167 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
12172 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
12174 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
12179 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
12289 /* Description: Enable UART */
12291 /* Bits 3..0 : Enable or disable UARTE */
12292 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12293 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12295 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
12472 /* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to…
12475 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
12492 /* Description: Enable interrupt */
12494 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
12499 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
12579 /* Description: Enable register for reload request registers */
12581 /* Bit 7 : Enable or disable RR[7] register */
12585 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
12587 /* Bit 6 : Enable or disable RR[6] register */
12591 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
12593 /* Bit 5 : Enable or disable RR[5] register */
12597 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
12599 /* Bit 4 : Enable or disable RR[4] register */
12603 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
12605 /* Bit 3 : Enable or disable RR[3] register */
12609 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
12611 /* Bit 2 : Enable or disable RR[2] register */
12615 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
12617 /* Bit 1 : Enable or disable RR[1] register */
12621 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
12623 /* Bit 0 : Enable or disable RR[0] register */
12627 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */