Lines Matching full:write

79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
86 /* Bit 1 : Write '1' to enable interrupt for RESOLVED event */
93 /* Bit 0 : Write '1' to enable interrupt for END event */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
110 /* Bit 1 : Write '1' to disable interrupt for RESOLVED event */
117 /* Bit 0 : Write '1' to disable interrupt for END event */
180 … cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. …
189 /* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */
195 /* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */
196 #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
197 #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
198 #define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */
199 #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */
266 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
273 /* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */
280 /* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */
290 /* Bit 2 : Write '1' to disable interrupt for ERROR event */
297 /* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */
304 /* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */
414 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_…
425 /* Bits 31..0 : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retai…
459 /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
563 /* Bit 11 : Write '1' to enable interrupt for CTSTOPPED event */
570 /* Bit 10 : Write '1' to enable interrupt for CTSTARTED event */
577 /* Bit 4 : Write '1' to enable interrupt for CTTO event */
584 /* Bit 3 : Write '1' to enable interrupt for DONE event */
591 /* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */
598 /* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */
608 /* Bit 11 : Write '1' to disable interrupt for CTSTOPPED event */
615 /* Bit 10 : Write '1' to disable interrupt for CTSTARTED event */
622 /* Bit 4 : Write '1' to disable interrupt for CTTO event */
629 /* Bit 3 : Write '1' to disable interrupt for DONE event */
636 /* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */
643 /* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */
896 /* Bit 3 : Write '1' to enable interrupt for CROSS event */
903 /* Bit 2 : Write '1' to enable interrupt for UP event */
910 /* Bit 1 : Write '1' to enable interrupt for DOWN event */
917 /* Bit 0 : Write '1' to enable interrupt for READY event */
927 /* Bit 3 : Write '1' to disable interrupt for CROSS event */
934 /* Bit 2 : Write '1' to disable interrupt for UP event */
941 /* Bit 1 : Write '1' to disable interrupt for DOWN event */
948 /* Bit 0 : Write '1' to disable interrupt for READY event */
1099 /* Bit 1 : Write '1' to enable interrupt for ERRORECB event */
1106 /* Bit 0 : Write '1' to enable interrupt for ENDECB event */
1116 /* Bit 1 : Write '1' to disable interrupt for ERRORECB event */
1123 /* Bit 0 : Write '1' to disable interrupt for ENDECB event */
1257 /* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */
1264 /* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */
1271 /* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */
1278 /* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */
1285 /* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */
1292 /* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */
1299 /* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */
1306 /* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */
1313 /* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */
1320 /* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */
1327 /* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */
1334 /* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */
1341 /* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */
1348 /* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */
1355 /* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */
1362 /* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */
1372 /* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */
1379 /* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */
1386 /* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */
1393 /* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */
1400 /* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */
1407 /* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */
1414 /* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */
1421 /* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */
1428 /* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */
1435 /* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */
1442 /* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */
1449 /* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */
1456 /* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */
1463 /* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */
1470 /* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */
1477 /* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */
1900 /* Bit 31 : Write '1' to enable interrupt for PORT event */
1907 /* Bit 7 : Write '1' to enable interrupt for IN[7] event */
1914 /* Bit 6 : Write '1' to enable interrupt for IN[6] event */
1921 /* Bit 5 : Write '1' to enable interrupt for IN[5] event */
1928 /* Bit 4 : Write '1' to enable interrupt for IN[4] event */
1935 /* Bit 3 : Write '1' to enable interrupt for IN[3] event */
1942 /* Bit 2 : Write '1' to enable interrupt for IN[2] event */
1949 /* Bit 1 : Write '1' to enable interrupt for IN[1] event */
1956 /* Bit 0 : Write '1' to enable interrupt for IN[0] event */
1966 /* Bit 31 : Write '1' to disable interrupt for PORT event */
1973 /* Bit 7 : Write '1' to disable interrupt for IN[7] event */
1980 /* Bit 6 : Write '1' to disable interrupt for IN[6] event */
1987 /* Bit 5 : Write '1' to disable interrupt for IN[5] event */
1994 /* Bit 4 : Write '1' to disable interrupt for IN[4] event */
2001 /* Bit 3 : Write '1' to disable interrupt for IN[3] event */
2008 /* Bit 2 : Write '1' to disable interrupt for IN[2] event */
2015 /* Bit 1 : Write '1' to disable interrupt for IN[1] event */
2022 /* Bit 0 : Write '1' to disable interrupt for IN[0] event */
2126 /* Bit 5 : Write '1' to enable interrupt for TXPTRUPD event */
2133 /* Bit 2 : Write '1' to enable interrupt for STOPPED event */
2140 /* Bit 1 : Write '1' to enable interrupt for RXPTRUPD event */
2150 /* Bit 5 : Write '1' to disable interrupt for TXPTRUPD event */
2157 /* Bit 2 : Write '1' to disable interrupt for STOPPED event */
2164 /* Bit 1 : Write '1' to disable interrupt for RXPTRUPD event */
2490 /* Bit 3 : Write '1' to enable interrupt for CROSS event */
2497 /* Bit 2 : Write '1' to enable interrupt for UP event */
2504 /* Bit 1 : Write '1' to enable interrupt for DOWN event */
2511 /* Bit 0 : Write '1' to enable interrupt for READY event */
2521 /* Bit 3 : Write '1' to disable interrupt for CROSS event */
2528 /* Bit 2 : Write '1' to disable interrupt for UP event */
2535 /* Bit 1 : Write '1' to disable interrupt for DOWN event */
2542 /* Bit 0 : Write '1' to disable interrupt for READY event */
2638 /* Description: Description cluster[n]: Write access to region n detected */
2652 /* Description: Description cluster[n]: Write access to peripheral region n detected */
2743 /* Bit 27 : Write '1' to enable interrupt for PREGION[1].RA event */
2750 /* Bit 26 : Write '1' to enable interrupt for PREGION[1].WA event */
2757 /* Bit 25 : Write '1' to enable interrupt for PREGION[0].RA event */
2764 /* Bit 24 : Write '1' to enable interrupt for PREGION[0].WA event */
2771 /* Bit 7 : Write '1' to enable interrupt for REGION[3].RA event */
2778 /* Bit 6 : Write '1' to enable interrupt for REGION[3].WA event */
2785 /* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */
2792 /* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */
2799 /* Bit 3 : Write '1' to enable interrupt for REGION[1].RA event */
2806 /* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */
2813 /* Bit 1 : Write '1' to enable interrupt for REGION[0].RA event */
2820 /* Bit 0 : Write '1' to enable interrupt for REGION[0].WA event */
2830 /* Bit 27 : Write '1' to disable interrupt for PREGION[1].RA event */
2837 /* Bit 26 : Write '1' to disable interrupt for PREGION[1].WA event */
2844 /* Bit 25 : Write '1' to disable interrupt for PREGION[0].RA event */
2851 /* Bit 24 : Write '1' to disable interrupt for PREGION[0].WA event */
2858 /* Bit 7 : Write '1' to disable interrupt for REGION[3].RA event */
2865 /* Bit 6 : Write '1' to disable interrupt for REGION[3].WA event */
2872 /* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */
2879 /* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */
2886 /* Bit 3 : Write '1' to disable interrupt for REGION[1].RA event */
2893 /* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */
2900 /* Bit 1 : Write '1' to disable interrupt for REGION[0].RA event */
2907 /* Bit 0 : Write '1' to disable interrupt for REGION[0].WA event */
2992 /* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */
2999 /* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */
3006 /* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */
3013 /* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */
3020 /* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */
3027 /* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */
3034 /* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */
3041 /* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */
3048 /* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */
3055 /* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */
3062 /* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */
3069 /* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */
3079 /* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */
3086 /* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */
3093 /* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */
3100 /* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */
3107 /* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */
3114 /* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */
3121 /* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */
3128 /* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */
3135 /* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */
3142 /* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */
3149 /* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */
3156 /* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */
3164 /* Description: Description cluster[n]: Source of event/interrupt in region n, write access detecte…
3166 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3169 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion…
3170 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion …
3172 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3175 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion…
3176 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion …
3178 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3181 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion…
3182 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion …
3184 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
3187 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion…
3188 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion …
3190 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
3193 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion…
3194 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion …
3196 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
3199 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion…
3200 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion …
3202 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
3205 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion…
3206 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion …
3208 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
3211 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion…
3212 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion …
3214 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
3217 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion…
3218 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion …
3220 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
3223 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion…
3224 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion …
3226 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
3229 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion…
3230 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion …
3232 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
3235 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion…
3236 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion …
3238 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
3241 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion…
3242 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion …
3244 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
3247 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion…
3248 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion …
3250 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
3253 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion…
3254 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion …
3256 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
3259 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion…
3260 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion …
3262 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
3265 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion…
3266 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion …
3268 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
3271 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion…
3272 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion …
3274 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
3277 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion…
3278 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion …
3280 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
3283 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion…
3284 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion …
3286 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
3289 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion…
3290 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion …
3292 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
3295 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion…
3296 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion …
3298 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
3301 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion …
3302 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3304 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
3307 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion …
3308 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3310 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
3313 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion …
3314 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3316 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
3319 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion …
3320 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3322 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
3325 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion …
3326 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3328 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
3331 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion …
3332 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3334 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
3337 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion …
3338 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3340 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3343 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion …
3344 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3346 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
3349 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion …
3350 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3352 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
3355 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion …
3356 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3361 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3367 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3373 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3379 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
3385 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
3391 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
3397 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
3403 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
3409 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
3415 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
3421 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
3427 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
3433 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
3439 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
3445 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
3451 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
3457 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
3463 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
3469 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
3475 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
3481 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
3487 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
3493 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
3499 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
3505 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
3511 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
3517 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
3523 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
3529 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
3535 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3541 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
3547 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
3562 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3565 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3566 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3574 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3577 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3578 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3586 /* Bit 6 : Enable/disable write access watch in region[3] */
3589 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3590 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3598 /* Bit 4 : Enable/disable write access watch in region[2] */
3601 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3602 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3610 /* Bit 2 : Enable/disable write access watch in region[1] */
3613 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3614 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3622 /* Bit 0 : Enable/disable write access watch in region[0] */
3625 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3626 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3638 /* Bit 26 : Enable write access watch in PREGION[1] */
3641 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3642 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3643 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3652 /* Bit 24 : Enable write access watch in PREGION[0] */
3655 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3656 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3657 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3666 /* Bit 6 : Enable write access watch in region[3] */
3669 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3670 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3671 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3680 /* Bit 4 : Enable write access watch in region[2] */
3683 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3684 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3685 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3694 /* Bit 2 : Enable write access watch in region[1] */
3697 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3698 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3699 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3708 /* Bit 0 : Enable write access watch in region[0] */
3711 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3712 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3713 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3725 /* Bit 26 : Disable write access watch in PREGION[1] */
3728 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3729 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3730 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3739 /* Bit 24 : Disable write access watch in PREGION[0] */
3742 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3743 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3744 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3753 /* Bit 6 : Disable write access watch in region[3] */
3756 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3757 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3758 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3767 /* Bit 4 : Disable write access watch in region[2] */
3770 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3771 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3772 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3781 /* Bit 2 : Disable write access watch in region[1] */
3784 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3785 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3786 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3795 /* Bit 0 : Disable write access watch in region[0] */
3798 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3799 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3800 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
4300 /* Bit 20 : Write '1' to enable interrupt for STARTED event */
4307 /* Bit 19 : Write '1' to enable interrupt for SELECTED event */
4314 /* Bit 18 : Write '1' to enable interrupt for COLLISION event */
4321 /* Bit 14 : Write '1' to enable interrupt for AUTOCOLRESSTARTED event */
4328 /* Bit 12 : Write '1' to enable interrupt for ENDTX event */
4335 /* Bit 11 : Write '1' to enable interrupt for ENDRX event */
4342 /* Bit 10 : Write '1' to enable interrupt for RXERROR event */
4349 /* Bit 7 : Write '1' to enable interrupt for ERROR event */
4356 /* Bit 6 : Write '1' to enable interrupt for RXFRAMEEND event */
4363 /* Bit 5 : Write '1' to enable interrupt for RXFRAMESTART event */
4370 /* Bit 4 : Write '1' to enable interrupt for TXFRAMEEND event */
4377 /* Bit 3 : Write '1' to enable interrupt for TXFRAMESTART event */
4384 /* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */
4391 /* Bit 1 : Write '1' to enable interrupt for FIELDDETECTED event */
4398 /* Bit 0 : Write '1' to enable interrupt for READY event */
4408 /* Bit 20 : Write '1' to disable interrupt for STARTED event */
4415 /* Bit 19 : Write '1' to disable interrupt for SELECTED event */
4422 /* Bit 18 : Write '1' to disable interrupt for COLLISION event */
4429 /* Bit 14 : Write '1' to disable interrupt for AUTOCOLRESSTARTED event */
4436 /* Bit 12 : Write '1' to disable interrupt for ENDTX event */
4443 /* Bit 11 : Write '1' to disable interrupt for ENDRX event */
4450 /* Bit 10 : Write '1' to disable interrupt for RXERROR event */
4457 /* Bit 7 : Write '1' to disable interrupt for ERROR event */
4464 /* Bit 6 : Write '1' to disable interrupt for RXFRAMEEND event */
4471 /* Bit 5 : Write '1' to disable interrupt for RXFRAMESTART event */
4478 /* Bit 4 : Write '1' to disable interrupt for TXFRAMEEND event */
4485 /* Bit 3 : Write '1' to disable interrupt for TXFRAMESTART event */
4492 /* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */
4499 /* Bit 1 : Write '1' to disable interrupt for FIELDDETECTED event */
4506 /* Bit 0 : Write '1' to disable interrupt for READY event */
4812 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4818 /* Bit 0 : NVMC can accept a new write operation */
4821 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
4827 … strongly recommended to only activate erase and write modes when they are actively used. Enabling…
4831 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
4921 /* Description: Write GPIO port */
5123 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5130 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5137 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5144 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5151 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5158 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5165 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5172 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5179 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5186 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5193 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5200 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5207 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5214 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5221 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5228 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5235 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5242 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5249 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5256 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5263 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5270 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5277 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5284 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5291 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5298 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5305 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5312 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5319 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5326 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5333 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5340 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5350 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5357 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5364 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5371 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5378 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5385 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5392 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5399 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5406 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5413 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5420 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5427 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5434 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5441 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5448 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5455 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5462 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5469 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5476 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5483 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5490 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5497 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5504 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5511 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5518 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5525 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5532 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5539 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5546 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5553 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5560 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5567 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5967 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5974 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5981 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5988 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5995 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6002 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6009 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6016 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6023 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6030 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6037 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6044 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6051 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6058 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6065 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6072 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6079 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6086 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6093 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6100 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6107 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6114 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6121 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6128 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6135 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6142 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6149 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6156 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6163 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6170 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6177 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6184 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6194 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6201 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6208 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6215 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6222 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6229 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6236 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6243 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6250 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6257 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6264 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6271 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6278 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6285 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6292 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6299 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6306 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6313 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6320 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6327 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6334 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6341 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6348 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6355 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6362 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6369 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6376 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6383 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6390 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6397 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6404 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6411 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6416 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to …
6422 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to …
6428 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to …
6434 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to …
6440 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to …
6446 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to …
6452 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to …
6458 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to …
6464 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to …
6470 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to …
6476 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to …
6482 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to …
6488 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to …
6494 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to …
6500 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to …
6506 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to …
6512 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to …
6518 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to …
6524 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to …
6530 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to …
6536 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to …
6542 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to …
6548 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to cle…
6554 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to cle…
6560 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to cle…
6566 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to cle…
6572 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to cle…
6578 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to cle…
6584 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to cle…
6590 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
6596 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to cle…
6602 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to cle…
6721 /* Bit 2 : Write '1' to enable interrupt for END event */
6728 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
6735 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
6745 /* Bit 2 : Write '1' to disable interrupt for END event */
6752 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
6759 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
6867 /* Description: RAM address pointer to write samples to with EasyDMA */
6869 /* Bits 31..0 : Address to write PDM samples to over DMA */
6943 /* Bit 9 : Write '1' to enable interrupt for USBPWRRDY event */
6950 /* Bit 8 : Write '1' to enable interrupt for USBREMOVED event */
6957 /* Bit 7 : Write '1' to enable interrupt for USBDETECTED event */
6964 /* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */
6971 /* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */
6978 /* Bit 2 : Write '1' to enable interrupt for POFWARN event */
6988 /* Bit 9 : Write '1' to disable interrupt for USBPWRRDY event */
6995 /* Bit 8 : Write '1' to disable interrupt for USBREMOVED event */
7002 /* Bit 7 : Write '1' to disable interrupt for USBDETECTED event */
7009 /* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */
7016 /* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */
7023 /* Bit 2 : Write '1' to disable interrupt for POFWARN event */
7965 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7972 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7979 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7986 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7993 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
8000 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
8007 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
8014 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
8021 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
8028 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
8035 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
8042 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
8049 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
8056 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
8063 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
8070 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
8077 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
8084 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
8091 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
8098 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
8105 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
8112 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
8119 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
8126 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
8133 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
8140 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
8147 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
8154 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
8161 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
8168 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
8175 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
8182 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
8192 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
8199 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
8206 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
8213 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
8220 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
8227 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
8234 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
8241 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
8248 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
8255 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
8262 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
8269 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
8276 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
8283 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
8290 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
8297 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
8304 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
8311 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
8318 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
8325 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
8332 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
8339 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
8346 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
8353 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
8360 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
8367 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
8374 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
8381 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
8388 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
8395 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
8402 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
8409 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
8768 /* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */
8775 /* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */
8782 /* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */
8789 /* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */
8796 /* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */
8803 /* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */
8810 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
8820 /* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */
8827 /* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */
8834 /* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */
8841 /* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */
8848 /* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */
8855 /* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */
8862 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
9103 /* Bit 4 : Write '1' to enable interrupt for STOPPED event */
9110 /* Bit 3 : Write '1' to enable interrupt for DBLRDY event */
9117 /* Bit 2 : Write '1' to enable interrupt for ACCOF event */
9124 /* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */
9131 /* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */
9141 /* Bit 4 : Write '1' to disable interrupt for STOPPED event */
9148 /* Bit 3 : Write '1' to disable interrupt for DBLRDY event */
9155 /* Bit 2 : Write '1' to disable interrupt for ACCOF event */
9162 /* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */
9169 /* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */
9388 /* Bit 0 : Write '1' to enable interrupt for READY event */
9398 /* Bit 0 : Write '1' to disable interrupt for READY event */
9450 /* Description: Write transfer length */
9452 /* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes.…
9676 /* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
9682 /* Bit 26 : Wait for write complete before sending command. */
9722 /* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
9728 /* Bit 14 : Wait for write complete before sending command. */
10173 /* Bit 27 : Write '1' to enable interrupt for PHYEND event */
10180 /* Bit 23 : Write '1' to enable interrupt for MHRMATCH event */
10187 /* Bit 22 : Write '1' to enable interrupt for RXREADY event */
10194 /* Bit 21 : Write '1' to enable interrupt for TXREADY event */
10201 /* Bit 20 : Write '1' to enable interrupt for RATEBOOST event */
10208 /* Bit 19 : Write '1' to enable interrupt for CCASTOPPED event */
10215 /* Bit 18 : Write '1' to enable interrupt for CCABUSY event */
10222 /* Bit 17 : Write '1' to enable interrupt for CCAIDLE event */
10229 /* Bit 16 : Write '1' to enable interrupt for EDSTOPPED event */
10236 /* Bit 15 : Write '1' to enable interrupt for EDEND event */
10243 /* Bit 14 : Write '1' to enable interrupt for FRAMESTART event */
10250 /* Bit 13 : Write '1' to enable interrupt for CRCERROR event */
10257 /* Bit 12 : Write '1' to enable interrupt for CRCOK event */
10264 /* Bit 10 : Write '1' to enable interrupt for BCMATCH event */
10271 /* Bit 7 : Write '1' to enable interrupt for RSSIEND event */
10278 /* Bit 6 : Write '1' to enable interrupt for DEVMISS event */
10285 /* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */
10292 /* Bit 4 : Write '1' to enable interrupt for DISABLED event */
10299 /* Bit 3 : Write '1' to enable interrupt for END event */
10306 /* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */
10313 /* Bit 1 : Write '1' to enable interrupt for ADDRESS event */
10320 /* Bit 0 : Write '1' to enable interrupt for READY event */
10330 /* Bit 27 : Write '1' to disable interrupt for PHYEND event */
10337 /* Bit 23 : Write '1' to disable interrupt for MHRMATCH event */
10344 /* Bit 22 : Write '1' to disable interrupt for RXREADY event */
10351 /* Bit 21 : Write '1' to disable interrupt for TXREADY event */
10358 /* Bit 20 : Write '1' to disable interrupt for RATEBOOST event */
10365 /* Bit 19 : Write '1' to disable interrupt for CCASTOPPED event */
10372 /* Bit 18 : Write '1' to disable interrupt for CCABUSY event */
10379 /* Bit 17 : Write '1' to disable interrupt for CCAIDLE event */
10386 /* Bit 16 : Write '1' to disable interrupt for EDSTOPPED event */
10393 /* Bit 15 : Write '1' to disable interrupt for EDEND event */
10400 /* Bit 14 : Write '1' to disable interrupt for FRAMESTART event */
10407 /* Bit 13 : Write '1' to disable interrupt for CRCERROR event */
10414 /* Bit 12 : Write '1' to disable interrupt for CRCOK event */
10421 /* Bit 10 : Write '1' to disable interrupt for BCMATCH event */
10428 /* Bit 7 : Write '1' to disable interrupt for RSSIEND event */
10435 /* Bit 6 : Write '1' to disable interrupt for DEVMISS event */
10442 /* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */
10449 /* Bit 4 : Write '1' to disable interrupt for DISABLED event */
10456 /* Bit 3 : Write '1' to disable interrupt for END event */
10463 /* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */
10470 /* Bit 1 : Write '1' to disable interrupt for ADDRESS event */
10477 /* Bit 0 : Write '1' to disable interrupt for READY event */
11045 /* Bit 0 : Write '1' to enable interrupt for VALRDY event */
11055 /* Bit 0 : Write '1' to disable interrupt for VALRDY event */
11134 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
11141 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
11148 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
11155 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
11162 /* Bit 1 : Write '1' to enable interrupt for OVRFLW event */
11169 /* Bit 0 : Write '1' to enable interrupt for TICK event */
11179 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
11186 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
11193 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
11200 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
11207 /* Bit 1 : Write '1' to disable interrupt for OVRFLW event */
11214 /* Bit 0 : Write '1' to disable interrupt for TICK event */
11263 /* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */
11270 /* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */
11277 /* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */
11284 /* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */
11291 /* Bit 1 : Write '1' to enable event routing for OVRFLW event */
11298 /* Bit 0 : Write '1' to enable event routing for TICK event */
11308 /* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */
11315 /* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */
11322 /* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */
11329 /* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */
11336 /* Bit 1 : Write '1' to disable event routing for OVRFLW event */
11343 /* Bit 0 : Write '1' to disable event routing for TICK event */
11597 /* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */
11604 /* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */
11611 /* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */
11618 /* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */
11625 /* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */
11632 /* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */
11639 /* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */
11646 /* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */
11653 /* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */
11660 /* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */
11667 /* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */
11674 /* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */
11681 /* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */
11688 /* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */
11695 /* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */
11702 /* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */
11709 /* Bit 5 : Write '1' to enable interrupt for STOPPED event */
11716 /* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */
11723 /* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */
11730 /* Bit 2 : Write '1' to enable interrupt for DONE event */
11737 /* Bit 1 : Write '1' to enable interrupt for END event */
11744 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
11754 /* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */
11761 /* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */
11768 /* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */
11775 /* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */
11782 /* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */
11789 /* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */
11796 /* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */
11803 /* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */
11810 /* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */
11817 /* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */
11824 /* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */
11831 /* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */
11838 /* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */
11845 /* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */
11852 /* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */
11859 /* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */
11866 /* Bit 5 : Write '1' to disable interrupt for STOPPED event */
11873 /* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */
11880 /* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */
11887 /* Bit 2 : Write '1' to disable interrupt for DONE event */
11894 /* Bit 1 : Write '1' to disable interrupt for END event */
11901 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
12107 /* Bit 2 : Write '1' to enable interrupt for READY event */
12117 /* Bit 2 : Write '1' to disable interrupt for READY event */
12312 /* Bit 19 : Write '1' to enable interrupt for STARTED event */
12319 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
12326 /* Bit 6 : Write '1' to enable interrupt for END event */
12333 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
12340 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
12350 /* Bit 19 : Write '1' to disable interrupt for STARTED event */
12357 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
12364 /* Bit 6 : Write '1' to disable interrupt for END event */
12371 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
12378 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
12679 /* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */
12686 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
12693 /* Bit 1 : Write '1' to enable interrupt for END event */
12703 /* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */
12710 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
12717 /* Bit 1 : Write '1' to disable interrupt for END event */
12743 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
12750 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
12934 /* Bit 0 : Write '1' to enable interrupt for DATARDY event */
12944 /* Bit 0 : Write '1' to disable interrupt for DATARDY event */
13208 /* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */
13215 /* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */
13222 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
13229 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
13236 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
13243 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
13253 /* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */
13260 /* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */
13267 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
13274 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
13281 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
13288 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
13429 /* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */
13436 /* Bit 14 : Write '1' to enable interrupt for BB event */
13443 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
13450 /* Bit 7 : Write '1' to enable interrupt for TXDSENT event */
13457 /* Bit 2 : Write '1' to enable interrupt for RXDREADY event */
13464 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
13474 /* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */
13481 /* Bit 14 : Write '1' to disable interrupt for BB event */
13488 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
13495 /* Bit 7 : Write '1' to disable interrupt for TXDSENT event */
13502 /* Bit 2 : Write '1' to disable interrupt for RXDREADY event */
13509 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
13519 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13525 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
13786 /* Bit 24 : Write '1' to enable interrupt for LASTTX event */
13793 /* Bit 23 : Write '1' to enable interrupt for LASTRX event */
13800 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
13807 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
13814 /* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */
13821 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
13828 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
13838 /* Bit 24 : Write '1' to disable interrupt for LASTTX event */
13845 /* Bit 23 : Write '1' to disable interrupt for LASTRX event */
13852 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
13859 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
13866 /* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */
13873 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
13880 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
13890 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13896 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
14054 /* Description: Prepare the TWI slave to respond to a write command */
14096 /* Description: Write command received */
14118 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
14133 /* Bit 25 : Enable or disable interrupt for WRITE event */
14134 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14135 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
14166 /* Bit 26 : Write '1' to enable interrupt for READ event */
14173 /* Bit 25 : Write '1' to enable interrupt for WRITE event */
14174 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14175 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
14180 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
14187 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
14194 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
14201 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
14211 /* Bit 26 : Write '1' to disable interrupt for READ event */
14218 /* Bit 25 : Write '1' to disable interrupt for WRITE event */
14219 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14220 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
14225 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
14232 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
14239 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
14246 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
14494 /* Bit 17 : Write '1' to enable interrupt for RXTO event */
14501 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
14508 /* Bit 7 : Write '1' to enable interrupt for TXDRDY event */
14515 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
14522 /* Bit 1 : Write '1' to enable interrupt for NCTS event */
14529 /* Bit 0 : Write '1' to enable interrupt for CTS event */
14539 /* Bit 17 : Write '1' to disable interrupt for RXTO event */
14546 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
14553 /* Bit 7 : Write '1' to disable interrupt for TXDRDY event */
14560 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
14567 /* Bit 1 : Write '1' to disable interrupt for NCTS event */
14574 /* Bit 0 : Write '1' to disable interrupt for CTS event */
14942 /* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */
14949 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
14956 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
14963 /* Bit 17 : Write '1' to enable interrupt for RXTO event */
14970 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
14977 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
14984 /* Bit 7 : Write '1' to enable interrupt for TXDRDY event */
14991 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
14998 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
15005 /* Bit 1 : Write '1' to enable interrupt for NCTS event */
15012 /* Bit 0 : Write '1' to enable interrupt for CTS event */
15022 /* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */
15029 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
15036 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
15043 /* Bit 17 : Write '1' to disable interrupt for RXTO event */
15050 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
15057 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
15064 /* Bit 7 : Write '1' to disable interrupt for TXDRDY event */
15071 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
15078 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
15085 /* Bit 1 : Write '1' to disable interrupt for NCTS event */
15092 /* Bit 0 : Write '1' to disable interrupt for CTS event */
15100 /* Description: Error source Note : this register is read / write one to clear. */
15713 /* Bit 24 : Write '1' to enable interrupt for EPDATA event */
15720 /* Bit 23 : Write '1' to enable interrupt for EP0SETUP event */
15727 /* Bit 22 : Write '1' to enable interrupt for USBEVENT event */
15734 /* Bit 21 : Write '1' to enable interrupt for SOF event */
15741 /* Bit 20 : Write '1' to enable interrupt for ENDISOOUT event */
15748 /* Bit 19 : Write '1' to enable interrupt for ENDEPOUT[7] event */
15755 /* Bit 18 : Write '1' to enable interrupt for ENDEPOUT[6] event */
15762 /* Bit 17 : Write '1' to enable interrupt for ENDEPOUT[5] event */
15769 /* Bit 16 : Write '1' to enable interrupt for ENDEPOUT[4] event */
15776 /* Bit 15 : Write '1' to enable interrupt for ENDEPOUT[3] event */
15783 /* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */
15790 /* Bit 13 : Write '1' to enable interrupt for ENDEPOUT[1] event */
15797 /* Bit 12 : Write '1' to enable interrupt for ENDEPOUT[0] event */
15804 /* Bit 11 : Write '1' to enable interrupt for ENDISOIN event */
15811 /* Bit 10 : Write '1' to enable interrupt for EP0DATADONE event */
15818 /* Bit 9 : Write '1' to enable interrupt for ENDEPIN[7] event */
15825 /* Bit 8 : Write '1' to enable interrupt for ENDEPIN[6] event */
15832 /* Bit 7 : Write '1' to enable interrupt for ENDEPIN[5] event */
15839 /* Bit 6 : Write '1' to enable interrupt for ENDEPIN[4] event */
15846 /* Bit 5 : Write '1' to enable interrupt for ENDEPIN[3] event */
15853 /* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */
15860 /* Bit 3 : Write '1' to enable interrupt for ENDEPIN[1] event */
15867 /* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */
15874 /* Bit 1 : Write '1' to enable interrupt for STARTED event */
15881 /* Bit 0 : Write '1' to enable interrupt for USBRESET event */
15891 /* Bit 24 : Write '1' to disable interrupt for EPDATA event */
15898 /* Bit 23 : Write '1' to disable interrupt for EP0SETUP event */
15905 /* Bit 22 : Write '1' to disable interrupt for USBEVENT event */
15912 /* Bit 21 : Write '1' to disable interrupt for SOF event */
15919 /* Bit 20 : Write '1' to disable interrupt for ENDISOOUT event */
15926 /* Bit 19 : Write '1' to disable interrupt for ENDEPOUT[7] event */
15933 /* Bit 18 : Write '1' to disable interrupt for ENDEPOUT[6] event */
15940 /* Bit 17 : Write '1' to disable interrupt for ENDEPOUT[5] event */
15947 /* Bit 16 : Write '1' to disable interrupt for ENDEPOUT[4] event */
15954 /* Bit 15 : Write '1' to disable interrupt for ENDEPOUT[3] event */
15961 /* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */
15968 /* Bit 13 : Write '1' to disable interrupt for ENDEPOUT[1] event */
15975 /* Bit 12 : Write '1' to disable interrupt for ENDEPOUT[0] event */
15982 /* Bit 11 : Write '1' to disable interrupt for ENDISOIN event */
15989 /* Bit 10 : Write '1' to disable interrupt for EP0DATADONE event */
15996 /* Bit 9 : Write '1' to disable interrupt for ENDEPIN[7] event */
16003 /* Bit 8 : Write '1' to disable interrupt for ENDEPIN[6] event */
16010 /* Bit 7 : Write '1' to disable interrupt for ENDEPIN[5] event */
16017 /* Bit 6 : Write '1' to disable interrupt for ENDEPIN[4] event */
16024 /* Bit 5 : Write '1' to disable interrupt for ENDEPIN[3] event */
16031 /* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */
16038 /* Bit 3 : Write '1' to disable interrupt for ENDEPIN[1] event */
16045 /* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */
16052 /* Bit 1 : Write '1' to disable interrupt for STARTED event */
16059 /* Bit 0 : Write '1' to disable interrupt for USBRESET event */
16069 /* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
16075 /* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
16081 …SUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
16087 /* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write…
16093 /* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
16120 /* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16126 /* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16132 /* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16138 /* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16144 /* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16150 /* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16156 /* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16162 /* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16168 /* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16174 /* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16180 /* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16186 /* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16192 /* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16198 /* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16204 /* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16210 /* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16216 /* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16222 /* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16231 /* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16237 /* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16243 /* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16249 /* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16255 /* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16261 /* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16267 /* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16273 /* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16279 /* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16285 /* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16291 /* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16297 /* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16303 /* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16309 /* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16629 #define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low po…
16630 #define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low powe…
16746 /* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */
16756 /* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */