Lines Matching full:enable

77 /* Description: Enable interrupt */
79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
84 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
86 /* Bit 1 : Write '1' to enable interrupt for RESOLVED event */
91 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
93 /* Bit 0 : Write '1' to enable interrupt for END event */
98 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
132 /* Description: Enable AAR */
134 /* Bits 1..0 : Enable or disable AAR */
135 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
136 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
138 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
261 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
264 /* Description: Enable interrupt */
266 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
271 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
273 /* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */
278 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
280 /* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */
285 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
321 /* Description: Enable */
323 /* Bits 1..0 : Enable or disable CCM */
324 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
325 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
327 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
561 /* Description: Enable interrupt */
563 /* Bit 11 : Write '1' to enable interrupt for CTSTOPPED event */
568 #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */
570 /* Bit 10 : Write '1' to enable interrupt for CTSTARTED event */
575 #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */
577 /* Bit 4 : Write '1' to enable interrupt for CTTO event */
582 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
584 /* Bit 3 : Write '1' to enable interrupt for DONE event */
589 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
591 /* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */
596 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
598 /* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */
603 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
712 /* Bit 17 : Enable or disable external source for LFCLK */
716 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (S…
718 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
722 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
840 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
846 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
852 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
858 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
864 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
867 /* Description: Enable or disable interrupt */
869 /* Bit 3 : Enable or disable interrupt for CROSS event */
873 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
875 /* Bit 2 : Enable or disable interrupt for UP event */
879 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
881 /* Bit 1 : Enable or disable interrupt for DOWN event */
885 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
887 /* Bit 0 : Enable or disable interrupt for READY event */
891 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
894 /* Description: Enable interrupt */
896 /* Bit 3 : Write '1' to enable interrupt for CROSS event */
901 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
903 /* Bit 2 : Write '1' to enable interrupt for UP event */
908 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
910 /* Bit 1 : Write '1' to enable interrupt for DOWN event */
915 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
917 /* Bit 0 : Write '1' to enable interrupt for READY event */
922 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
965 /* Description: COMP enable */
967 /* Bits 1..0 : Enable or disable COMP */
968 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
969 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
971 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1043 /* Description: Comparator hysteresis enable */
1056 /* Description: Enable CRYPTOCELL subsystem */
1058 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
1059 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1060 …PTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1097 /* Description: Enable interrupt */
1099 /* Bit 1 : Write '1' to enable interrupt for ERRORECB event */
1104 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1106 /* Bit 0 : Write '1' to enable interrupt for ENDECB event */
1111 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1156 /* Description: Enable or disable interrupt */
1158 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1162 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1164 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1168 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1170 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1174 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1176 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1180 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1182 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1186 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1188 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1192 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1194 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1198 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1200 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1204 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1206 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1210 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1212 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1216 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1218 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1222 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1224 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1228 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1230 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1234 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1236 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1240 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1242 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1246 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1248 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1252 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1255 /* Description: Enable interrupt */
1257 /* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */
1262 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1264 /* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */
1269 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1271 /* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */
1276 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1278 /* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */
1283 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1285 /* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */
1290 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1292 /* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */
1297 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1299 /* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */
1304 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1306 /* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */
1311 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1313 /* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */
1318 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1320 /* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */
1325 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1327 /* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */
1332 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1334 /* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */
1339 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1341 /* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */
1346 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1348 /* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */
1353 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1355 /* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */
1360 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1362 /* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */
1367 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1898 /* Description: Enable interrupt */
1900 /* Bit 31 : Write '1' to enable interrupt for PORT event */
1905 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1907 /* Bit 7 : Write '1' to enable interrupt for IN[7] event */
1912 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1914 /* Bit 6 : Write '1' to enable interrupt for IN[6] event */
1919 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1921 /* Bit 5 : Write '1' to enable interrupt for IN[5] event */
1926 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1928 /* Bit 4 : Write '1' to enable interrupt for IN[4] event */
1933 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1935 /* Bit 3 : Write '1' to enable interrupt for IN[3] event */
1940 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1942 /* Bit 2 : Write '1' to enable interrupt for IN[2] event */
1947 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1949 /* Bit 1 : Write '1' to enable interrupt for IN[1] event */
1954 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1956 /* Bit 0 : Write '1' to enable interrupt for IN[0] event */
1961 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2103 /* Description: Enable or disable interrupt */
2105 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
2109 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2111 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2115 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2117 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2121 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2124 /* Description: Enable interrupt */
2126 /* Bit 5 : Write '1' to enable interrupt for TXPTRUPD event */
2131 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2133 /* Bit 2 : Write '1' to enable interrupt for STOPPED event */
2138 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2140 /* Bit 1 : Write '1' to enable interrupt for RXPTRUPD event */
2145 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2172 /* Description: Enable I2S module. */
2174 /* Bit 0 : Enable I2S module. */
2175 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2176 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2178 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2190 /* Description: Reception (RX) enable. */
2192 /* Bit 0 : Reception (RX) enable. */
2199 /* Description: Transmission (TX) enable. */
2201 /* Bit 0 : Transmission (TX) enable. */
2208 /* Description: Master clock generator enable. */
2210 /* Bit 0 : Master clock generator enable. */
2286 /* Description: Enable channels. */
2288 /* Bits 1..0 : Enable channels. */
2461 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2467 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2473 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2479 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2485 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2488 /* Description: Enable interrupt */
2490 /* Bit 3 : Write '1' to enable interrupt for CROSS event */
2495 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2497 /* Bit 2 : Write '1' to enable interrupt for UP event */
2502 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2504 /* Bit 1 : Write '1' to enable interrupt for DOWN event */
2509 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2511 /* Bit 0 : Write '1' to enable interrupt for READY event */
2516 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2559 /* Description: Enable LPCOMP */
2561 /* Bits 1..0 : Enable or disable LPCOMP */
2562 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2563 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.…
2565 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2625 /* Description: Comparator hysteresis enable */
2627 /* Bit 0 : Comparator hysteresis enable */
2666 /* Description: Enable or disable interrupt */
2668 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2672 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2674 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2678 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2680 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
2684 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2686 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
2690 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2692 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
2696 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2698 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
2702 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2704 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2708 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2710 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2714 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2716 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2720 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2722 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2726 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2728 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2732 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2734 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
2738 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2741 /* Description: Enable interrupt */
2743 /* Bit 27 : Write '1' to enable interrupt for PREGION[1].RA event */
2748 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2750 /* Bit 26 : Write '1' to enable interrupt for PREGION[1].WA event */
2755 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2757 /* Bit 25 : Write '1' to enable interrupt for PREGION[0].RA event */
2762 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2764 /* Bit 24 : Write '1' to enable interrupt for PREGION[0].WA event */
2769 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2771 /* Bit 7 : Write '1' to enable interrupt for REGION[3].RA event */
2776 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2778 /* Bit 6 : Write '1' to enable interrupt for REGION[3].WA event */
2783 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2785 /* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */
2790 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2792 /* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */
2797 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2799 /* Bit 3 : Write '1' to enable interrupt for REGION[1].RA event */
2804 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2806 /* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */
2811 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2813 /* Bit 1 : Write '1' to enable interrupt for REGION[0].RA event */
2818 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2820 /* Bit 0 : Write '1' to enable interrupt for REGION[0].WA event */
2825 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
2915 /* Description: Enable or disable non-maskable interrupt */
2917 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
2921 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2923 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
2927 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2929 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
2933 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2935 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
2939 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2941 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
2945 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
2947 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
2951 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
2953 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
2957 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
2959 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
2963 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
2965 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
2969 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
2971 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
2975 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
2977 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
2981 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
2983 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
2987 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
2990 /* Description: Enable non-maskable interrupt */
2992 /* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */
2997 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
2999 /* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */
3004 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3006 /* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */
3011 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3013 /* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */
3018 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3020 /* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */
3025 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3027 /* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */
3032 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3034 /* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */
3039 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3041 /* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */
3046 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3048 /* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */
3053 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3055 /* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */
3060 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3062 /* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */
3067 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3069 /* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */
3074 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3554 /* Description: Enable/disable regions watch */
3556 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3560 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3562 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3566 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3568 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3572 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3574 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3578 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3580 /* Bit 7 : Enable/disable read access watch in region[3] */
3584 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3586 /* Bit 6 : Enable/disable write access watch in region[3] */
3590 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3592 /* Bit 5 : Enable/disable read access watch in region[2] */
3596 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3598 /* Bit 4 : Enable/disable write access watch in region[2] */
3602 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3604 /* Bit 3 : Enable/disable read access watch in region[1] */
3608 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3610 /* Bit 2 : Enable/disable write access watch in region[1] */
3614 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3616 /* Bit 1 : Enable/disable read access watch in region[0] */
3620 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3622 /* Bit 0 : Enable/disable write access watch in region[0] */
3626 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3629 /* Description: Enable regions watch */
3631 /* Bit 27 : Enable read access watch in PREGION[1] */
3636 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3638 /* Bit 26 : Enable write access watch in PREGION[1] */
3643 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3645 /* Bit 25 : Enable read access watch in PREGION[0] */
3650 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3652 /* Bit 24 : Enable write access watch in PREGION[0] */
3657 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3659 /* Bit 7 : Enable read access watch in region[3] */
3664 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3666 /* Bit 6 : Enable write access watch in region[3] */
3671 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3673 /* Bit 5 : Enable read access watch in region[2] */
3678 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3680 /* Bit 4 : Enable write access watch in region[2] */
3685 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3687 /* Bit 3 : Enable read access watch in region[1] */
3692 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3694 /* Bit 2 : Enable write access watch in region[1] */
3699 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3701 /* Bit 1 : Enable read access watch in region[0] */
3706 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3708 /* Bit 0 : Enable write access watch in region[0] */
3713 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
4044 /* Description: Enable NFC sense field mode, change state to sense mode */
4190 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */
4196 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4202 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4205 /* Description: Enable or disable interrupt */
4207 /* Bit 20 : Enable or disable interrupt for STARTED event */
4211 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4213 /* Bit 19 : Enable or disable interrupt for SELECTED event */
4217 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4219 /* Bit 18 : Enable or disable interrupt for COLLISION event */
4223 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4225 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
4229 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4231 /* Bit 12 : Enable or disable interrupt for ENDTX event */
4235 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4237 /* Bit 11 : Enable or disable interrupt for ENDRX event */
4241 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4243 /* Bit 10 : Enable or disable interrupt for RXERROR event */
4247 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4249 /* Bit 7 : Enable or disable interrupt for ERROR event */
4253 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4255 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
4259 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4261 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
4265 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4267 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
4271 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4273 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
4277 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4279 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4283 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4285 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4289 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4291 /* Bit 0 : Enable or disable interrupt for READY event */
4295 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4298 /* Description: Enable interrupt */
4300 /* Bit 20 : Write '1' to enable interrupt for STARTED event */
4305 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4307 /* Bit 19 : Write '1' to enable interrupt for SELECTED event */
4312 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4314 /* Bit 18 : Write '1' to enable interrupt for COLLISION event */
4319 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4321 /* Bit 14 : Write '1' to enable interrupt for AUTOCOLRESSTARTED event */
4326 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4328 /* Bit 12 : Write '1' to enable interrupt for ENDTX event */
4333 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4335 /* Bit 11 : Write '1' to enable interrupt for ENDRX event */
4340 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4342 /* Bit 10 : Write '1' to enable interrupt for RXERROR event */
4347 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4349 /* Bit 7 : Write '1' to enable interrupt for ERROR event */
4354 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4356 /* Bit 6 : Write '1' to enable interrupt for RXFRAMEEND event */
4361 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4363 /* Bit 5 : Write '1' to enable interrupt for RXFRAMESTART event */
4368 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4370 /* Bit 4 : Write '1' to enable interrupt for TXFRAMEEND event */
4375 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4377 /* Bit 3 : Write '1' to enable interrupt for TXFRAMESTART event */
4382 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4384 /* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */
4389 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4391 /* Bit 1 : Write '1' to enable interrupt for FIELDDETECTED event */
4396 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4398 /* Bit 0 : Write '1' to enable interrupt for READY event */
4403 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4890 /* Bit 8 : Cache profiling enable */
4894 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4896 /* Bit 0 : Cache enable */
4900 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
6698 /* Description: Enable or disable interrupt */
6700 /* Bit 2 : Enable or disable interrupt for END event */
6704 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6706 /* Bit 1 : Enable or disable interrupt for STOPPED event */
6710 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6712 /* Bit 0 : Enable or disable interrupt for STARTED event */
6716 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6719 /* Description: Enable interrupt */
6721 /* Bit 2 : Write '1' to enable interrupt for END event */
6726 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6728 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
6733 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6735 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
6740 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6767 /* Description: PDM module enable register */
6769 /* Bit 0 : Enable or disable PDM module */
6770 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6771 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6773 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6885 /* Description: Enable constant latency mode */
6892 /* Description: Enable low power mode (variable latency) */
6941 /* Description: Enable interrupt */
6943 /* Bit 9 : Write '1' to enable interrupt for USBPWRRDY event */
6948 #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
6950 /* Bit 8 : Write '1' to enable interrupt for USBREMOVED event */
6955 #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
6957 /* Bit 7 : Write '1' to enable interrupt for USBDETECTED event */
6962 #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
6964 /* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */
6969 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
6971 /* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */
6976 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
6978 /* Bit 2 : Write '1' to enable interrupt for POFWARN event */
6983 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
7132 /* Bit 0 : Enable System OFF mode */
7135 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
7176 /* Bit 0 : Enable or disable power failure warning */
7180 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
7197 /* Description: Enable DC/DC converter for REG1 stage. */
7199 /* Bit 0 : Enable DC/DC converter for REG1 stage. */
7203 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
7206 /* Description: Enable DC/DC converter for REG0 stage. */
7208 /* Bit 0 : Enable DC/DC converter for REG0 stage. */
7212 #define POWER_DCDCEN0_DCDCEN_Enabled (1UL) /*!< Enable */
7749 /* Description: Description cluster[n]: Enable channel group n */
7763 /* Description: Channel enable register */
7765 /* Bit 31 : Enable or disable channel 31 */
7769 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7771 /* Bit 30 : Enable or disable channel 30 */
7775 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7777 /* Bit 29 : Enable or disable channel 29 */
7781 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7783 /* Bit 28 : Enable or disable channel 28 */
7787 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7789 /* Bit 27 : Enable or disable channel 27 */
7793 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7795 /* Bit 26 : Enable or disable channel 26 */
7799 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7801 /* Bit 25 : Enable or disable channel 25 */
7805 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7807 /* Bit 24 : Enable or disable channel 24 */
7811 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7813 /* Bit 23 : Enable or disable channel 23 */
7817 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7819 /* Bit 22 : Enable or disable channel 22 */
7823 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7825 /* Bit 21 : Enable or disable channel 21 */
7829 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7831 /* Bit 20 : Enable or disable channel 20 */
7835 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7837 /* Bit 19 : Enable or disable channel 19 */
7841 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7843 /* Bit 18 : Enable or disable channel 18 */
7847 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7849 /* Bit 17 : Enable or disable channel 17 */
7853 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7855 /* Bit 16 : Enable or disable channel 16 */
7859 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7861 /* Bit 15 : Enable or disable channel 15 */
7865 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7867 /* Bit 14 : Enable or disable channel 14 */
7871 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7873 /* Bit 13 : Enable or disable channel 13 */
7877 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7879 /* Bit 12 : Enable or disable channel 12 */
7883 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7885 /* Bit 11 : Enable or disable channel 11 */
7889 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7891 /* Bit 10 : Enable or disable channel 10 */
7895 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7897 /* Bit 9 : Enable or disable channel 9 */
7901 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
7903 /* Bit 8 : Enable or disable channel 8 */
7907 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
7909 /* Bit 7 : Enable or disable channel 7 */
7913 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
7915 /* Bit 6 : Enable or disable channel 6 */
7919 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
7921 /* Bit 5 : Enable or disable channel 5 */
7925 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
7927 /* Bit 4 : Enable or disable channel 4 */
7931 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
7933 /* Bit 3 : Enable or disable channel 3 */
7937 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
7939 /* Bit 2 : Enable or disable channel 2 */
7943 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
7945 /* Bit 1 : Enable or disable channel 1 */
7949 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
7951 /* Bit 0 : Enable or disable channel 0 */
7955 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
7958 /* Description: Channel enable set register */
7960 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
7965 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7967 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
7972 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7974 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
7979 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7981 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
7986 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7988 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
7993 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
7995 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
8000 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
8002 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
8007 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
8009 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
8014 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
8016 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
8021 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
8023 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
8028 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
8030 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
8035 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
8037 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
8042 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
8044 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
8049 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
8051 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
8056 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
8058 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
8063 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
8065 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
8070 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
8072 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
8077 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
8079 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
8084 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
8086 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
8091 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
8093 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
8098 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
8100 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
8105 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
8107 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
8112 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
8114 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
8119 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
8121 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
8126 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
8128 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
8133 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
8135 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
8140 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
8142 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
8147 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
8149 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
8154 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
8156 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
8161 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
8163 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
8168 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
8170 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
8175 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
8177 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
8182 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
8185 /* Description: Channel enable clear register */
8187 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
8194 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
8201 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
8208 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
8215 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
8222 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
8229 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
8236 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
8243 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
8250 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
8257 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
8264 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
8271 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
8278 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
8285 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
8292 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
8299 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
8306 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
8313 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
8320 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
8327 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
8334 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
8341 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
8348 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
8355 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
8362 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
8369 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
8376 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
8383 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
8390 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
8397 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
8404 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
8694 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
8700 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
8706 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
8712 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
8718 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
8721 /* Description: Enable or disable interrupt */
8723 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
8727 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
8729 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
8733 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
8735 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
8739 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
8741 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
8745 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
8747 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
8751 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
8753 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
8757 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
8759 /* Bit 1 : Enable or disable interrupt for STOPPED event */
8763 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8766 /* Description: Enable interrupt */
8768 /* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */
8773 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8775 /* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */
8780 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8782 /* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */
8787 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8789 /* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */
8794 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8796 /* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */
8801 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8803 /* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */
8808 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
8810 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
8815 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8870 /* Description: PWM module enable register */
8872 /* Bit 0 : Enable or disable PWM module */
8873 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8874 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8876 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9062 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9068 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9074 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
9080 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9086 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
9092 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9098 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9101 /* Description: Enable interrupt */
9103 /* Bit 4 : Write '1' to enable interrupt for STOPPED event */
9108 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9110 /* Bit 3 : Write '1' to enable interrupt for DBLRDY event */
9115 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
9117 /* Bit 2 : Write '1' to enable interrupt for ACCOF event */
9122 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
9124 /* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */
9129 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
9131 /* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */
9136 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
9177 /* Description: Enable the quadrature decoder */
9179 /* Bit 0 : Enable or disable the quadrature decoder */
9180 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9181 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9183 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9301 /* Description: Enable input debounce filters */
9303 /* Bit 0 : Enable input debounce filters */
9377 /* Description: Enable or disable interrupt */
9379 /* Bit 0 : Enable or disable interrupt for READY event */
9383 #define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */
9386 /* Description: Enable interrupt */
9388 /* Bit 0 : Write '1' to enable interrupt for READY event */
9393 #define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */
9406 /* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */
9408 /* Bit 0 : Enable or disable QSPI */
9409 #define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9410 #define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9412 #define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */
9591 /* Bit 7 : Enable deep power-down mode (DPM) feature. */
9595 #define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */
9676 /* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
9716 /* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended …
9722 /* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
9809 /* Description: Enable RADIO in TX mode */
9816 /* Description: Enable RADIO in RX mode */
10060 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
10066 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10072 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
10078 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
10084 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
10090 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10096 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
10102 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
10108 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10114 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
10120 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
10126 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
10132 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
10138 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
10144 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
10150 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
10156 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
10162 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10168 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
10171 /* Description: Enable interrupt */
10173 /* Bit 27 : Write '1' to enable interrupt for PHYEND event */
10178 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
10180 /* Bit 23 : Write '1' to enable interrupt for MHRMATCH event */
10185 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
10187 /* Bit 22 : Write '1' to enable interrupt for RXREADY event */
10192 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
10194 /* Bit 21 : Write '1' to enable interrupt for TXREADY event */
10199 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
10201 /* Bit 20 : Write '1' to enable interrupt for RATEBOOST event */
10206 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
10208 /* Bit 19 : Write '1' to enable interrupt for CCASTOPPED event */
10213 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
10215 /* Bit 18 : Write '1' to enable interrupt for CCABUSY event */
10220 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
10222 /* Bit 17 : Write '1' to enable interrupt for CCAIDLE event */
10227 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
10229 /* Bit 16 : Write '1' to enable interrupt for EDSTOPPED event */
10234 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
10236 /* Bit 15 : Write '1' to enable interrupt for EDEND event */
10241 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
10243 /* Bit 14 : Write '1' to enable interrupt for FRAMESTART event */
10248 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
10250 /* Bit 13 : Write '1' to enable interrupt for CRCERROR event */
10255 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
10257 /* Bit 12 : Write '1' to enable interrupt for CRCOK event */
10262 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
10264 /* Bit 10 : Write '1' to enable interrupt for BCMATCH event */
10269 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
10271 /* Bit 7 : Write '1' to enable interrupt for RSSIEND event */
10276 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
10278 /* Bit 6 : Write '1' to enable interrupt for DEVMISS event */
10283 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
10285 /* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */
10290 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
10292 /* Bit 4 : Write '1' to enable interrupt for DISABLED event */
10297 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
10299 /* Bit 3 : Write '1' to enable interrupt for END event */
10304 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
10306 /* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */
10311 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
10313 /* Bit 1 : Write '1' to enable interrupt for ADDRESS event */
10318 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
10320 /* Bit 0 : Write '1' to enable interrupt for READY event */
10325 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
10631 /* Bit 25 : Enable or disable packet whitening */
10635 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
10717 /* Bit 7 : Enable or disable reception on logical address 7. */
10721 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
10723 /* Bit 6 : Enable or disable reception on logical address 6. */
10727 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
10729 /* Bit 5 : Enable or disable reception on logical address 5. */
10733 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
10735 /* Bit 4 : Enable or disable reception on logical address 4. */
10739 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
10741 /* Bit 3 : Enable or disable reception on logical address 3. */
10745 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
10747 /* Bit 2 : Enable or disable reception on logical address 2. */
10751 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
10753 /* Bit 1 : Enable or disable reception on logical address 1. */
10757 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
10759 /* Bit 0 : Enable or disable reception on logical address 0. */
10763 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
10890 /* Bit 7 : Enable or disable device address matching using device address 7 */
10896 /* Bit 6 : Enable or disable device address matching using device address 6 */
10902 /* Bit 5 : Enable or disable device address matching using device address 5 */
10908 /* Bit 4 : Enable or disable device address matching using device address 4 */
10914 /* Bit 3 : Enable or disable device address matching using device address 3 */
10920 /* Bit 2 : Enable or disable device address matching using device address 2 */
10926 /* Bit 1 : Enable or disable device address matching using device address 1 */
10932 /* Bit 0 : Enable or disable device address matching using device address 0 */
11040 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
11043 /* Description: Enable interrupt */
11045 /* Bit 0 : Write '1' to enable interrupt for VALRDY event */
11050 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
11132 /* Description: Enable interrupt */
11134 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
11139 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
11141 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
11146 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
11148 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
11153 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
11155 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
11160 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
11162 /* Bit 1 : Write '1' to enable interrupt for OVRFLW event */
11167 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
11169 /* Bit 0 : Write '1' to enable interrupt for TICK event */
11174 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
11222 /* Description: Enable or disable event routing */
11224 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
11228 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
11230 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
11234 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
11236 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
11240 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
11242 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
11246 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
11248 /* Bit 1 : Enable or disable event routing for OVRFLW event */
11252 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
11254 /* Bit 0 : Enable or disable event routing for TICK event */
11258 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
11261 /* Description: Enable event routing */
11263 /* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */
11268 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
11270 /* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */
11275 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
11277 /* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */
11282 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
11284 /* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */
11289 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
11291 /* Bit 1 : Write '1' to enable event routing for OVRFLW event */
11296 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
11298 /* Bit 0 : Write '1' to enable event routing for TICK event */
11303 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
11460 /* Description: Enable or disable interrupt */
11462 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
11466 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
11468 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
11472 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
11474 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
11478 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
11480 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
11484 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
11486 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
11490 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
11492 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
11496 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
11498 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
11502 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
11504 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
11508 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
11510 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
11514 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
11516 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
11520 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
11522 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
11526 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
11528 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
11532 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
11534 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
11538 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
11540 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
11544 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
11546 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
11550 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
11552 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
11556 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
11558 /* Bit 5 : Enable or disable interrupt for STOPPED event */
11562 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11564 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
11568 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
11570 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
11574 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
11576 /* Bit 2 : Enable or disable interrupt for DONE event */
11580 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
11582 /* Bit 1 : Enable or disable interrupt for END event */
11586 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
11588 /* Bit 0 : Enable or disable interrupt for STARTED event */
11592 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
11595 /* Description: Enable interrupt */
11597 /* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */
11602 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
11604 /* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */
11609 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
11611 /* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */
11616 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
11618 /* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */
11623 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
11625 /* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */
11630 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
11632 /* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */
11637 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
11639 /* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */
11644 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
11646 /* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */
11651 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
11653 /* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */
11658 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
11660 /* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */
11665 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
11667 /* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */
11672 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
11674 /* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */
11679 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
11681 /* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */
11686 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
11688 /* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */
11693 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
11695 /* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */
11700 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
11702 /* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */
11707 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
11709 /* Bit 5 : Write '1' to enable interrupt for STOPPED event */
11714 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11716 /* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */
11721 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
11723 /* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */
11728 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
11730 /* Bit 2 : Write '1' to enable interrupt for DONE event */
11735 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
11737 /* Bit 1 : Write '1' to enable interrupt for END event */
11742 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
11744 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
11749 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
11918 /* Description: Enable or disable SAADC */
11920 /* Bit 0 : Enable or disable SAADC */
11921 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11922 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11924 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */
11965 /* Bit 24 : Enable burst mode */
11971 /* Bit 20 : Enable differential mode */
12105 /* Description: Enable interrupt */
12107 /* Bit 2 : Write '1' to enable interrupt for READY event */
12112 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
12125 /* Description: Enable SPI */
12127 /* Bits 3..0 : Enable or disable SPI */
12128 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12129 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12131 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
12307 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
12310 /* Description: Enable interrupt */
12312 /* Bit 19 : Write '1' to enable interrupt for STARTED event */
12317 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
12319 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
12324 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12326 /* Bit 6 : Write '1' to enable interrupt for END event */
12331 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
12333 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
12338 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12340 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
12345 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
12401 /* Description: Enable SPIM */
12403 /* Bits 3..0 : Enable or disable SPIM */
12404 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12405 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12407 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
12674 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
12677 /* Description: Enable interrupt */
12679 /* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */
12684 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
12686 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
12691 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12693 /* Bit 1 : Write '1' to enable interrupt for END event */
12698 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
12753 /* Description: Enable SPI slave */
12755 /* Bits 3..0 : Enable or disable SPI slave */
12756 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12757 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12759 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
12932 /* Description: Enable interrupt */
12934 /* Bit 0 : Write '1' to enable interrupt for DATARDY event */
12939 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
13137 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
13143 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
13149 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
13155 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
13161 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
13167 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
13173 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13179 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13185 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13191 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13197 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13203 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13206 /* Description: Enable interrupt */
13208 /* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */
13213 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
13215 /* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */
13220 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
13222 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
13227 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
13229 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
13234 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
13236 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
13241 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
13243 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
13248 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
13418 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
13424 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13427 /* Description: Enable interrupt */
13429 /* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */
13434 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
13436 /* Bit 14 : Write '1' to enable interrupt for BB event */
13441 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
13443 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
13448 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
13450 /* Bit 7 : Write '1' to enable interrupt for TXDSENT event */
13455 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
13457 /* Bit 2 : Write '1' to enable interrupt for RXDREADY event */
13462 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
13464 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
13469 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
13538 /* Description: Enable TWI */
13540 /* Bits 3..0 : Enable or disable TWI */
13541 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13542 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13544 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
13706 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
13712 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13718 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
13724 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
13730 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13736 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
13739 /* Description: Enable or disable interrupt */
13741 /* Bit 24 : Enable or disable interrupt for LASTTX event */
13745 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
13747 /* Bit 23 : Enable or disable interrupt for LASTRX event */
13751 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
13753 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
13757 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
13759 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
13763 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
13765 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
13769 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
13771 /* Bit 9 : Enable or disable interrupt for ERROR event */
13775 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
13777 /* Bit 1 : Enable or disable interrupt for STOPPED event */
13781 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
13784 /* Description: Enable interrupt */
13786 /* Bit 24 : Write '1' to enable interrupt for LASTTX event */
13791 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
13793 /* Bit 23 : Write '1' to enable interrupt for LASTRX event */
13798 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
13800 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
13805 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
13807 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
13812 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
13814 /* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */
13819 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
13821 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
13826 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
13828 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
13833 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
13909 /* Description: Enable TWIM */
13911 /* Bits 3..0 : Enable or disable TWIM */
13912 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13913 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13915 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
14116 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14122 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14125 /* Description: Enable or disable interrupt */
14127 /* Bit 26 : Enable or disable interrupt for READ event */
14131 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
14133 /* Bit 25 : Enable or disable interrupt for WRITE event */
14137 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
14139 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
14143 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
14145 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
14149 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
14151 /* Bit 9 : Enable or disable interrupt for ERROR event */
14155 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
14157 /* Bit 1 : Enable or disable interrupt for STOPPED event */
14161 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
14164 /* Description: Enable interrupt */
14166 /* Bit 26 : Write '1' to enable interrupt for READ event */
14171 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
14173 /* Bit 25 : Write '1' to enable interrupt for WRITE event */
14178 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
14180 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
14185 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
14187 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
14192 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
14194 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
14199 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
14201 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
14206 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
14282 /* Description: Enable TWIS */
14284 /* Bits 3..0 : Enable or disable TWIS */
14285 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14286 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14288 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
14376 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
14382 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
14483 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
14489 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
14492 /* Description: Enable interrupt */
14494 /* Bit 17 : Write '1' to enable interrupt for RXTO event */
14499 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
14501 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
14506 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
14508 /* Bit 7 : Write '1' to enable interrupt for TXDRDY event */
14513 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
14515 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
14520 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
14522 /* Bit 1 : Write '1' to enable interrupt for NCTS event */
14527 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
14529 /* Bit 0 : Write '1' to enable interrupt for CTS event */
14534 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
14609 /* Description: Enable UART */
14611 /* Bits 3..0 : Enable or disable UART */
14612 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14613 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14615 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
14862 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
14868 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
14871 /* Description: Enable or disable interrupt */
14873 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
14877 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
14879 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
14883 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
14885 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
14889 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
14891 /* Bit 17 : Enable or disable interrupt for RXTO event */
14895 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
14897 /* Bit 9 : Enable or disable interrupt for ERROR event */
14901 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
14903 /* Bit 8 : Enable or disable interrupt for ENDTX event */
14907 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
14909 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
14913 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
14915 /* Bit 4 : Enable or disable interrupt for ENDRX event */
14919 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
14921 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
14925 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
14927 /* Bit 1 : Enable or disable interrupt for NCTS event */
14931 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
14933 /* Bit 0 : Enable or disable interrupt for CTS event */
14937 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
14940 /* Description: Enable interrupt */
14942 /* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */
14947 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
14949 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
14954 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
14956 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
14961 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
14963 /* Bit 17 : Write '1' to enable interrupt for RXTO event */
14968 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
14970 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
14975 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
14977 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
14982 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
14984 /* Bit 7 : Write '1' to enable interrupt for TXDRDY event */
14989 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
14991 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
14996 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
14998 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
15003 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
15005 /* Bit 1 : Write '1' to enable interrupt for NCTS event */
15010 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
15012 /* Bit 0 : Write '1' to enable interrupt for CTS event */
15017 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
15127 /* Description: Enable UART */
15129 /* Bits 3..0 : Enable or disable UARTE */
15130 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15131 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15133 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
15336 /* Bits 7..0 : Enable or disable access port protection. */
15339 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
15358 #define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */
15364 #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default…
15531 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
15537 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
15543 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
15549 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
15555 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
15558 /* Description: Enable or disable interrupt */
15560 /* Bit 24 : Enable or disable interrupt for EPDATA event */
15564 #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
15566 /* Bit 23 : Enable or disable interrupt for EP0SETUP event */
15570 #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
15572 /* Bit 22 : Enable or disable interrupt for USBEVENT event */
15576 #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
15578 /* Bit 21 : Enable or disable interrupt for SOF event */
15582 #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
15584 /* Bit 20 : Enable or disable interrupt for ENDISOOUT event */
15588 #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
15590 /* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */
15594 #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
15596 /* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */
15600 #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
15602 /* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */
15606 #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
15608 /* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */
15612 #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
15614 /* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */
15618 #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
15620 /* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */
15624 #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
15626 /* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */
15630 #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
15632 /* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */
15636 #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
15638 /* Bit 11 : Enable or disable interrupt for ENDISOIN event */
15642 #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
15644 /* Bit 10 : Enable or disable interrupt for EP0DATADONE event */
15648 #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
15650 /* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */
15654 #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
15656 /* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */
15660 #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
15662 /* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */
15666 #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
15668 /* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */
15672 #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
15674 /* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */
15678 #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
15680 /* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */
15684 #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
15686 /* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */
15690 #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
15692 /* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */
15696 #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
15698 /* Bit 1 : Enable or disable interrupt for STARTED event */
15702 #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
15704 /* Bit 0 : Enable or disable interrupt for USBRESET event */
15708 #define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
15711 /* Description: Enable interrupt */
15713 /* Bit 24 : Write '1' to enable interrupt for EPDATA event */
15718 #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
15720 /* Bit 23 : Write '1' to enable interrupt for EP0SETUP event */
15725 #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
15727 /* Bit 22 : Write '1' to enable interrupt for USBEVENT event */
15732 #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
15734 /* Bit 21 : Write '1' to enable interrupt for SOF event */
15739 #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
15741 /* Bit 20 : Write '1' to enable interrupt for ENDISOOUT event */
15746 #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
15748 /* Bit 19 : Write '1' to enable interrupt for ENDEPOUT[7] event */
15753 #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
15755 /* Bit 18 : Write '1' to enable interrupt for ENDEPOUT[6] event */
15760 #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
15762 /* Bit 17 : Write '1' to enable interrupt for ENDEPOUT[5] event */
15767 #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
15769 /* Bit 16 : Write '1' to enable interrupt for ENDEPOUT[4] event */
15774 #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
15776 /* Bit 15 : Write '1' to enable interrupt for ENDEPOUT[3] event */
15781 #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
15783 /* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */
15788 #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
15790 /* Bit 13 : Write '1' to enable interrupt for ENDEPOUT[1] event */
15795 #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
15797 /* Bit 12 : Write '1' to enable interrupt for ENDEPOUT[0] event */
15802 #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
15804 /* Bit 11 : Write '1' to enable interrupt for ENDISOIN event */
15809 #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
15811 /* Bit 10 : Write '1' to enable interrupt for EP0DATADONE event */
15816 #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
15818 /* Bit 9 : Write '1' to enable interrupt for ENDEPIN[7] event */
15823 #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
15825 /* Bit 8 : Write '1' to enable interrupt for ENDEPIN[6] event */
15830 #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
15832 /* Bit 7 : Write '1' to enable interrupt for ENDEPIN[5] event */
15837 #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
15839 /* Bit 6 : Write '1' to enable interrupt for ENDEPIN[4] event */
15844 #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
15846 /* Bit 5 : Write '1' to enable interrupt for ENDEPIN[3] event */
15851 #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
15853 /* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */
15858 #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
15860 /* Bit 3 : Write '1' to enable interrupt for ENDEPIN[1] event */
15865 #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
15867 /* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */
15872 #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
15874 /* Bit 1 : Write '1' to enable interrupt for STARTED event */
15879 #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
15881 /* Bit 0 : Write '1' to enable interrupt for USBRESET event */
15886 #define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
16427 /* Description: Enable USB */
16429 /* Bit 0 : Enable USB */
16430 #define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
16431 #define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
16475 /* Description: Endpoint IN enable */
16477 /* Bit 8 : Enable ISO IN endpoint */
16481 #define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */
16483 /* Bit 7 : Enable IN endpoint 7 */
16487 #define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
16489 /* Bit 6 : Enable IN endpoint 6 */
16493 #define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
16495 /* Bit 5 : Enable IN endpoint 5 */
16499 #define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
16501 /* Bit 4 : Enable IN endpoint 4 */
16505 #define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
16507 /* Bit 3 : Enable IN endpoint 3 */
16511 #define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
16513 /* Bit 2 : Enable IN endpoint 2 */
16517 #define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
16519 /* Bit 1 : Enable IN endpoint 1 */
16523 #define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
16525 /* Bit 0 : Enable IN endpoint 0 */
16529 #define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
16532 /* Description: Endpoint OUT enable */
16534 /* Bit 8 : Enable ISO OUT endpoint 8 */
16538 #define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */
16540 /* Bit 7 : Enable OUT endpoint 7 */
16544 #define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
16546 /* Bit 6 : Enable OUT endpoint 6 */
16550 #define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
16552 /* Bit 5 : Enable OUT endpoint 5 */
16556 #define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
16558 /* Bit 4 : Enable OUT endpoint 4 */
16562 #define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
16564 /* Bit 3 : Enable OUT endpoint 3 */
16568 #define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
16570 /* Bit 2 : Enable OUT endpoint 2 */
16574 #define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
16576 /* Bit 1 : Enable OUT endpoint 1 */
16580 #define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
16582 /* Bit 0 : Enable OUT endpoint 0 */
16586 #define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
16744 /* Description: Enable interrupt */
16746 /* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */
16751 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
16831 /* Description: Enable register for reload request registers */
16833 /* Bit 7 : Enable or disable RR[7] register */
16837 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
16839 /* Bit 6 : Enable or disable RR[6] register */
16843 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
16845 /* Bit 5 : Enable or disable RR[5] register */
16849 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
16851 /* Bit 4 : Enable or disable RR[4] register */
16855 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
16857 /* Bit 3 : Enable or disable RR[3] register */
16861 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
16863 /* Bit 2 : Enable or disable RR[2] register */
16867 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
16869 /* Bit 1 : Enable or disable RR[1] register */
16873 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
16875 /* Bit 0 : Enable or disable RR[0] register */
16879 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */