Lines Matching full:disable

101 /* Description: Disable interrupt */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
108 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
110 /* Bit 1 : Write '1' to disable interrupt for RESOLVED event */
115 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
117 /* Bit 0 : Write '1' to disable interrupt for END event */
122 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
134 /* Bits 1..0 : Enable or disable AAR */
137 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
260 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
288 /* Description: Disable interrupt */
290 /* Bit 2 : Write '1' to disable interrupt for ERROR event */
295 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
297 /* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */
302 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
304 /* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */
309 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
323 /* Bits 1..0 : Enable or disable CCM */
326 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
606 /* Description: Disable interrupt */
608 /* Bit 11 : Write '1' to disable interrupt for CTSTOPPED event */
613 #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */
615 /* Bit 10 : Write '1' to disable interrupt for CTSTARTED event */
620 #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */
622 /* Bit 4 : Write '1' to disable interrupt for CTTO event */
627 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
629 /* Bit 3 : Write '1' to disable interrupt for DONE event */
634 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
636 /* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */
641 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
643 /* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */
648 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
712 /* Bit 17 : Enable or disable external source for LFCLK */
715 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
718 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
721 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external sour…
839 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
845 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
851 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
857 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
863 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
867 /* Description: Enable or disable interrupt */
869 /* Bit 3 : Enable or disable interrupt for CROSS event */
872 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
875 /* Bit 2 : Enable or disable interrupt for UP event */
878 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
881 /* Bit 1 : Enable or disable interrupt for DOWN event */
884 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
887 /* Bit 0 : Enable or disable interrupt for READY event */
890 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
925 /* Description: Disable interrupt */
927 /* Bit 3 : Write '1' to disable interrupt for CROSS event */
932 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
934 /* Bit 2 : Write '1' to disable interrupt for UP event */
939 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
941 /* Bit 1 : Write '1' to disable interrupt for DOWN event */
946 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
948 /* Bit 0 : Write '1' to disable interrupt for READY event */
953 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
967 /* Bits 1..0 : Enable or disable COMP */
970 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1058 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
1114 /* Description: Disable interrupt */
1116 /* Bit 1 : Write '1' to disable interrupt for ERRORECB event */
1121 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1123 /* Bit 0 : Write '1' to disable interrupt for ENDECB event */
1128 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1156 /* Description: Enable or disable interrupt */
1158 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1161 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1164 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1167 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1170 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1173 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1176 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1179 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1182 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1185 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1188 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1191 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1194 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1197 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1200 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1203 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1206 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1209 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1212 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1215 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1218 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1221 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1224 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1227 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1230 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1233 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1236 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1239 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1242 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1245 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1248 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1251 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1370 /* Description: Disable interrupt */
1372 /* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */
1377 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1379 /* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */
1384 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1386 /* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */
1391 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1393 /* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */
1398 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1400 /* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */
1405 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1407 /* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */
1412 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1414 /* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */
1419 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1421 /* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */
1426 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1428 /* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */
1433 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1435 /* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */
1440 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1442 /* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */
1447 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1449 /* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */
1454 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1456 /* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */
1461 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1463 /* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */
1468 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1470 /* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */
1475 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1477 /* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */
1482 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1964 /* Description: Disable interrupt */
1966 /* Bit 31 : Write '1' to disable interrupt for PORT event */
1971 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1973 /* Bit 7 : Write '1' to disable interrupt for IN[7] event */
1978 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1980 /* Bit 6 : Write '1' to disable interrupt for IN[6] event */
1985 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1987 /* Bit 5 : Write '1' to disable interrupt for IN[5] event */
1992 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1994 /* Bit 4 : Write '1' to disable interrupt for IN[4] event */
1999 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2001 /* Bit 3 : Write '1' to disable interrupt for IN[3] event */
2006 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2008 /* Bit 2 : Write '1' to disable interrupt for IN[2] event */
2013 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2015 /* Bit 1 : Write '1' to disable interrupt for IN[1] event */
2020 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2022 /* Bit 0 : Write '1' to disable interrupt for IN[0] event */
2027 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2103 /* Description: Enable or disable interrupt */
2105 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
2108 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2111 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2114 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2117 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2120 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2148 /* Description: Disable interrupt */
2150 /* Bit 5 : Write '1' to disable interrupt for TXPTRUPD event */
2155 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2157 /* Bit 2 : Write '1' to disable interrupt for STOPPED event */
2162 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2164 /* Bit 1 : Write '1' to disable interrupt for RXPTRUPD event */
2169 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2177 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2460 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
2466 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
2472 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
2478 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
2484 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
2519 /* Description: Disable interrupt */
2521 /* Bit 3 : Write '1' to disable interrupt for CROSS event */
2526 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2528 /* Bit 2 : Write '1' to disable interrupt for UP event */
2533 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2535 /* Bit 1 : Write '1' to disable interrupt for DOWN event */
2540 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2542 /* Bit 0 : Write '1' to disable interrupt for READY event */
2547 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2561 /* Bits 1..0 : Enable or disable LPCOMP */
2564 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2666 /* Description: Enable or disable interrupt */
2668 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2671 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2674 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2677 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2680 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
2683 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2686 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
2689 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2692 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
2695 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
2698 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
2701 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
2704 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2707 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
2710 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2713 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
2716 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2719 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
2722 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2725 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
2728 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2731 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
2734 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
2737 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
2828 /* Description: Disable interrupt */
2830 /* Bit 27 : Write '1' to disable interrupt for PREGION[1].RA event */
2835 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2837 /* Bit 26 : Write '1' to disable interrupt for PREGION[1].WA event */
2842 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2844 /* Bit 25 : Write '1' to disable interrupt for PREGION[0].RA event */
2849 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2851 /* Bit 24 : Write '1' to disable interrupt for PREGION[0].WA event */
2856 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2858 /* Bit 7 : Write '1' to disable interrupt for REGION[3].RA event */
2863 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2865 /* Bit 6 : Write '1' to disable interrupt for REGION[3].WA event */
2870 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
2872 /* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */
2877 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
2879 /* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */
2884 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
2886 /* Bit 3 : Write '1' to disable interrupt for REGION[1].RA event */
2891 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
2893 /* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */
2898 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
2900 /* Bit 1 : Write '1' to disable interrupt for REGION[0].RA event */
2905 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
2907 /* Bit 0 : Write '1' to disable interrupt for REGION[0].WA event */
2912 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
2915 /* Description: Enable or disable non-maskable interrupt */
2917 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
2920 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2923 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
2926 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2929 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
2932 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2935 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
2938 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2941 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
2944 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
2947 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
2950 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
2953 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
2956 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
2959 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
2962 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
2965 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
2968 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
2971 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
2974 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
2977 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
2980 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
2983 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
2986 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
3077 /* Description: Disable non-maskable interrupt */
3079 /* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */
3084 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3086 /* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */
3091 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3093 /* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */
3098 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3100 /* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */
3105 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3107 /* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */
3112 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3114 /* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */
3119 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3121 /* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */
3126 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3128 /* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */
3133 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3135 /* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */
3140 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3142 /* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */
3147 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3149 /* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */
3154 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3156 /* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */
3161 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3554 /* Description: Enable/disable regions watch */
3556 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3559 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3562 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3565 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3568 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3571 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3574 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3577 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3580 /* Bit 7 : Enable/disable read access watch in region[3] */
3583 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3586 /* Bit 6 : Enable/disable write access watch in region[3] */
3589 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3592 /* Bit 5 : Enable/disable read access watch in region[2] */
3595 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3598 /* Bit 4 : Enable/disable write access watch in region[2] */
3601 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3604 /* Bit 3 : Enable/disable read access watch in region[1] */
3607 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3610 /* Bit 2 : Enable/disable write access watch in region[1] */
3613 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3616 /* Bit 1 : Enable/disable read access watch in region[0] */
3619 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3622 /* Bit 0 : Enable/disable write access watch in region[0] */
3625 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3716 /* Description: Disable regions watch */
3718 /* Bit 27 : Disable read access watch in PREGION[1] */
3723 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3725 /* Bit 26 : Disable write access watch in PREGION[1] */
3730 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3732 /* Bit 25 : Disable read access watch in PREGION[0] */
3737 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3739 /* Bit 24 : Disable write access watch in PREGION[0] */
3744 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3746 /* Bit 7 : Disable read access watch in region[3] */
3751 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3753 /* Bit 6 : Disable write access watch in region[3] */
3758 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3760 /* Bit 5 : Disable read access watch in region[2] */
3765 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3767 /* Bit 4 : Disable write access watch in region[2] */
3772 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3774 /* Bit 3 : Disable read access watch in region[1] */
3779 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3781 /* Bit 2 : Disable write access watch in region[1] */
3786 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3788 /* Bit 1 : Disable read access watch in region[0] */
3793 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3795 /* Bit 0 : Disable write access watch in region[0] */
3800 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
4037 /* Description: Disable NFCT peripheral */
4189 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */
4195 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4201 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4205 /* Description: Enable or disable interrupt */
4207 /* Bit 20 : Enable or disable interrupt for STARTED event */
4210 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4213 /* Bit 19 : Enable or disable interrupt for SELECTED event */
4216 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4219 /* Bit 18 : Enable or disable interrupt for COLLISION event */
4222 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4225 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
4228 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4231 /* Bit 12 : Enable or disable interrupt for ENDTX event */
4234 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4237 /* Bit 11 : Enable or disable interrupt for ENDRX event */
4240 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4243 /* Bit 10 : Enable or disable interrupt for RXERROR event */
4246 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4249 /* Bit 7 : Enable or disable interrupt for ERROR event */
4252 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4255 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
4258 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4261 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
4264 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4267 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
4270 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4273 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
4276 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4279 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4282 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4285 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4288 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4291 /* Bit 0 : Enable or disable interrupt for READY event */
4294 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4406 /* Description: Disable interrupt */
4408 /* Bit 20 : Write '1' to disable interrupt for STARTED event */
4413 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4415 /* Bit 19 : Write '1' to disable interrupt for SELECTED event */
4420 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4422 /* Bit 18 : Write '1' to disable interrupt for COLLISION event */
4427 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4429 /* Bit 14 : Write '1' to disable interrupt for AUTOCOLRESSTARTED event */
4434 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4436 /* Bit 12 : Write '1' to disable interrupt for ENDTX event */
4441 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4443 /* Bit 11 : Write '1' to disable interrupt for ENDRX event */
4448 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4450 /* Bit 10 : Write '1' to disable interrupt for RXERROR event */
4455 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4457 /* Bit 7 : Write '1' to disable interrupt for ERROR event */
4462 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4464 /* Bit 6 : Write '1' to disable interrupt for RXFRAMEEND event */
4469 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4471 /* Bit 5 : Write '1' to disable interrupt for RXFRAMESTART event */
4476 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4478 /* Bit 4 : Write '1' to disable interrupt for TXFRAMEEND event */
4483 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4485 /* Bit 3 : Write '1' to disable interrupt for TXFRAMESTART event */
4490 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4492 /* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */
4497 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4499 /* Bit 1 : Write '1' to disable interrupt for FIELDDETECTED event */
4504 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4506 /* Bit 0 : Write '1' to disable interrupt for READY event */
4511 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4893 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
4899 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
6698 /* Description: Enable or disable interrupt */
6700 /* Bit 2 : Enable or disable interrupt for END event */
6703 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
6706 /* Bit 1 : Enable or disable interrupt for STOPPED event */
6709 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6712 /* Bit 0 : Enable or disable interrupt for STARTED event */
6715 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6743 /* Description: Disable interrupt */
6745 /* Bit 2 : Write '1' to disable interrupt for END event */
6750 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6752 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
6757 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6759 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
6764 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6769 /* Bit 0 : Enable or disable PDM module */
6772 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
6986 /* Description: Disable interrupt */
6988 /* Bit 9 : Write '1' to disable interrupt for USBPWRRDY event */
6993 #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
6995 /* Bit 8 : Write '1' to disable interrupt for USBREMOVED event */
7000 #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
7002 /* Bit 7 : Write '1' to disable interrupt for USBDETECTED event */
7007 #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
7009 /* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */
7014 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
7016 /* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */
7021 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
7023 /* Bit 2 : Write '1' to disable interrupt for POFWARN event */
7028 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
7176 /* Bit 0 : Enable or disable power failure warning */
7179 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
7202 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
7211 #define POWER_DCDCEN0_DCDCEN_Disabled (0UL) /*!< Disable */
7756 /* Description: Description cluster[n]: Disable channel group n */
7765 /* Bit 31 : Enable or disable channel 31 */
7768 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7771 /* Bit 30 : Enable or disable channel 30 */
7774 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7777 /* Bit 29 : Enable or disable channel 29 */
7780 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7783 /* Bit 28 : Enable or disable channel 28 */
7786 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7789 /* Bit 27 : Enable or disable channel 27 */
7792 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7795 /* Bit 26 : Enable or disable channel 26 */
7798 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7801 /* Bit 25 : Enable or disable channel 25 */
7804 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7807 /* Bit 24 : Enable or disable channel 24 */
7810 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7813 /* Bit 23 : Enable or disable channel 23 */
7816 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7819 /* Bit 22 : Enable or disable channel 22 */
7822 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
7825 /* Bit 21 : Enable or disable channel 21 */
7828 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
7831 /* Bit 20 : Enable or disable channel 20 */
7834 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
7837 /* Bit 19 : Enable or disable channel 19 */
7840 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
7843 /* Bit 18 : Enable or disable channel 18 */
7846 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
7849 /* Bit 17 : Enable or disable channel 17 */
7852 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
7855 /* Bit 16 : Enable or disable channel 16 */
7858 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
7861 /* Bit 15 : Enable or disable channel 15 */
7864 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
7867 /* Bit 14 : Enable or disable channel 14 */
7870 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
7873 /* Bit 13 : Enable or disable channel 13 */
7876 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
7879 /* Bit 12 : Enable or disable channel 12 */
7882 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
7885 /* Bit 11 : Enable or disable channel 11 */
7888 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
7891 /* Bit 10 : Enable or disable channel 10 */
7894 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
7897 /* Bit 9 : Enable or disable channel 9 */
7900 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
7903 /* Bit 8 : Enable or disable channel 8 */
7906 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
7909 /* Bit 7 : Enable or disable channel 7 */
7912 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
7915 /* Bit 6 : Enable or disable channel 6 */
7918 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
7921 /* Bit 5 : Enable or disable channel 5 */
7924 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
7927 /* Bit 4 : Enable or disable channel 4 */
7930 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
7933 /* Bit 3 : Enable or disable channel 3 */
7936 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
7939 /* Bit 2 : Enable or disable channel 2 */
7942 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
7945 /* Bit 1 : Enable or disable channel 1 */
7948 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
7951 /* Bit 0 : Enable or disable channel 0 */
7954 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
8192 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
8199 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
8206 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
8213 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
8220 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
8227 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
8234 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
8241 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
8248 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
8255 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
8262 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
8269 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
8276 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
8283 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
8290 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
8297 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
8304 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
8311 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
8318 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
8325 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
8332 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
8339 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
8346 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
8353 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
8360 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
8367 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
8374 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
8381 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
8388 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
8395 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
8402 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
8409 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
8693 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
8699 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
8705 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
8711 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
8717 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
8721 /* Description: Enable or disable interrupt */
8723 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
8726 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
8729 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
8732 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
8735 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
8738 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
8741 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
8744 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
8747 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
8750 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
8753 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
8756 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
8759 /* Bit 1 : Enable or disable interrupt for STOPPED event */
8762 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8818 /* Description: Disable interrupt */
8820 /* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */
8825 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
8827 /* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */
8832 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
8834 /* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */
8839 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
8841 /* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */
8846 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
8848 /* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */
8853 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
8855 /* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */
8860 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
8862 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
8867 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8872 /* Bit 0 : Enable or disable PWM module */
9061 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9067 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9073 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
9079 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9085 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
9091 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9097 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9139 /* Description: Disable interrupt */
9141 /* Bit 4 : Write '1' to disable interrupt for STOPPED event */
9146 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9148 /* Bit 3 : Write '1' to disable interrupt for DBLRDY event */
9153 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
9155 /* Bit 2 : Write '1' to disable interrupt for ACCOF event */
9160 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
9162 /* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */
9167 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
9169 /* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */
9174 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
9179 /* Bit 0 : Enable or disable the quadrature decoder */
9182 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
9377 /* Description: Enable or disable interrupt */
9379 /* Bit 0 : Enable or disable interrupt for READY event */
9382 #define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */
9396 /* Description: Disable interrupt */
9398 /* Bit 0 : Write '1' to disable interrupt for READY event */
9403 #define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
9408 /* Bit 0 : Enable or disable QSPI */
9411 #define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */
9594 #define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */
9837 /* Description: Disable RADIO */
10059 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
10062 /* Bit 20 : Shortcut between PHYEND event and DISABLE task */
10065 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10071 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
10077 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
10083 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
10086 /* Bit 16 : Shortcut between EDEND event and DISABLE task */
10089 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10095 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
10101 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
10104 /* Bit 13 : Shortcut between CCABUSY event and DISABLE task */
10107 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10113 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
10119 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
10125 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
10131 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
10137 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
10143 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
10149 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
10155 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
10158 /* Bit 1 : Shortcut between END event and DISABLE task */
10161 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10167 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
10328 /* Description: Disable interrupt */
10330 /* Bit 27 : Write '1' to disable interrupt for PHYEND event */
10335 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
10337 /* Bit 23 : Write '1' to disable interrupt for MHRMATCH event */
10342 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
10344 /* Bit 22 : Write '1' to disable interrupt for RXREADY event */
10349 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
10351 /* Bit 21 : Write '1' to disable interrupt for TXREADY event */
10356 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
10358 /* Bit 20 : Write '1' to disable interrupt for RATEBOOST event */
10363 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
10365 /* Bit 19 : Write '1' to disable interrupt for CCASTOPPED event */
10370 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
10372 /* Bit 18 : Write '1' to disable interrupt for CCABUSY event */
10377 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
10379 /* Bit 17 : Write '1' to disable interrupt for CCAIDLE event */
10384 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
10386 /* Bit 16 : Write '1' to disable interrupt for EDSTOPPED event */
10391 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
10393 /* Bit 15 : Write '1' to disable interrupt for EDEND event */
10398 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
10400 /* Bit 14 : Write '1' to disable interrupt for FRAMESTART event */
10405 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
10407 /* Bit 13 : Write '1' to disable interrupt for CRCERROR event */
10412 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
10414 /* Bit 12 : Write '1' to disable interrupt for CRCOK event */
10419 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
10421 /* Bit 10 : Write '1' to disable interrupt for BCMATCH event */
10426 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
10428 /* Bit 7 : Write '1' to disable interrupt for RSSIEND event */
10433 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
10435 /* Bit 6 : Write '1' to disable interrupt for DEVMISS event */
10440 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
10442 /* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */
10447 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
10449 /* Bit 4 : Write '1' to disable interrupt for DISABLED event */
10454 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
10456 /* Bit 3 : Write '1' to disable interrupt for END event */
10461 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
10463 /* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */
10468 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
10470 /* Bit 1 : Write '1' to disable interrupt for ADDRESS event */
10475 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
10477 /* Bit 0 : Write '1' to disable interrupt for READY event */
10482 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
10631 /* Bit 25 : Enable or disable packet whitening */
10634 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
10717 /* Bit 7 : Enable or disable reception on logical address 7. */
10720 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
10723 /* Bit 6 : Enable or disable reception on logical address 6. */
10726 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
10729 /* Bit 5 : Enable or disable reception on logical address 5. */
10732 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
10735 /* Bit 4 : Enable or disable reception on logical address 4. */
10738 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
10741 /* Bit 3 : Enable or disable reception on logical address 3. */
10744 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
10747 /* Bit 2 : Enable or disable reception on logical address 2. */
10750 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
10753 /* Bit 1 : Enable or disable reception on logical address 1. */
10756 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
10759 /* Bit 0 : Enable or disable reception on logical address 0. */
10762 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
10890 /* Bit 7 : Enable or disable device address matching using device address 7 */
10896 /* Bit 6 : Enable or disable device address matching using device address 6 */
10902 /* Bit 5 : Enable or disable device address matching using device address 5 */
10908 /* Bit 4 : Enable or disable device address matching using device address 4 */
10914 /* Bit 3 : Enable or disable device address matching using device address 3 */
10920 /* Bit 2 : Enable or disable device address matching using device address 2 */
10926 /* Bit 1 : Enable or disable device address matching using device address 1 */
10932 /* Bit 0 : Enable or disable device address matching using device address 0 */
11039 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
11053 /* Description: Disable interrupt */
11055 /* Bit 0 : Write '1' to disable interrupt for VALRDY event */
11060 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
11177 /* Description: Disable interrupt */
11179 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
11184 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11186 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
11191 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11193 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
11198 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11200 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
11205 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11207 /* Bit 1 : Write '1' to disable interrupt for OVRFLW event */
11212 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11214 /* Bit 0 : Write '1' to disable interrupt for TICK event */
11219 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
11222 /* Description: Enable or disable event routing */
11224 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
11227 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
11230 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
11233 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
11236 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
11239 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
11242 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
11245 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
11248 /* Bit 1 : Enable or disable event routing for OVRFLW event */
11251 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
11254 /* Bit 0 : Enable or disable event routing for TICK event */
11257 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
11306 /* Description: Disable event routing */
11308 /* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */
11313 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11315 /* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */
11320 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11322 /* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */
11327 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11329 /* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */
11334 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11336 /* Bit 1 : Write '1' to disable event routing for OVRFLW event */
11341 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11343 /* Bit 0 : Write '1' to disable event routing for TICK event */
11348 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
11460 /* Description: Enable or disable interrupt */
11462 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
11465 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
11468 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
11471 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
11474 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
11477 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
11480 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
11483 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
11486 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
11489 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
11492 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
11495 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
11498 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
11501 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
11504 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
11507 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
11510 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
11513 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
11516 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
11519 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
11522 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
11525 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
11528 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
11531 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
11534 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
11537 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
11540 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
11543 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
11546 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
11549 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
11552 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
11555 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
11558 /* Bit 5 : Enable or disable interrupt for STOPPED event */
11561 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11564 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
11567 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
11570 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
11573 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
11576 /* Bit 2 : Enable or disable interrupt for DONE event */
11579 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
11582 /* Bit 1 : Enable or disable interrupt for END event */
11585 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
11588 /* Bit 0 : Enable or disable interrupt for STARTED event */
11591 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
11752 /* Description: Disable interrupt */
11754 /* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */
11759 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
11761 /* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */
11766 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
11768 /* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */
11773 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
11775 /* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */
11780 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
11782 /* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */
11787 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
11789 /* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */
11794 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
11796 /* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */
11801 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
11803 /* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */
11808 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
11810 /* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */
11815 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
11817 /* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */
11822 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
11824 /* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */
11829 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
11831 /* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */
11836 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
11838 /* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */
11843 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
11845 /* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */
11850 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
11852 /* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */
11857 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
11859 /* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */
11864 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
11866 /* Bit 5 : Write '1' to disable interrupt for STOPPED event */
11871 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11873 /* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */
11878 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
11880 /* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */
11885 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
11887 /* Bit 2 : Write '1' to disable interrupt for DONE event */
11892 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
11894 /* Bit 1 : Write '1' to disable interrupt for END event */
11899 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
11901 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
11906 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
11918 /* Description: Enable or disable SAADC */
11920 /* Bit 0 : Enable or disable SAADC */
11923 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */
12115 /* Description: Disable interrupt */
12117 /* Bit 2 : Write '1' to disable interrupt for READY event */
12122 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
12127 /* Bits 3..0 : Enable or disable SPI */
12130 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
12306 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
12348 /* Description: Disable interrupt */
12350 /* Bit 19 : Write '1' to disable interrupt for STARTED event */
12355 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
12357 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
12362 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12364 /* Bit 6 : Write '1' to disable interrupt for END event */
12369 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
12371 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
12376 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12378 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
12383 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12403 /* Bits 3..0 : Enable or disable SPIM */
12406 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
12520 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12550 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12673 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
12701 /* Description: Disable interrupt */
12703 /* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */
12708 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
12710 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
12715 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12717 /* Bit 1 : Write '1' to disable interrupt for END event */
12722 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
12755 /* Bits 3..0 : Enable or disable SPI slave */
12758 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
12942 /* Description: Disable interrupt */
12944 /* Bit 0 : Write '1' to disable interrupt for DATARDY event */
12949 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
13136 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
13142 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
13148 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
13154 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
13160 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
13166 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
13172 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13178 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13184 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13190 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13196 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13202 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13251 /* Description: Disable interrupt */
13253 /* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */
13258 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
13260 /* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */
13265 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
13267 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
13272 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
13274 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
13279 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
13281 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
13286 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
13288 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
13293 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
13417 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
13423 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13472 /* Description: Disable interrupt */
13474 /* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */
13479 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
13481 /* Bit 14 : Write '1' to disable interrupt for BB event */
13486 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
13488 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
13493 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13495 /* Bit 7 : Write '1' to disable interrupt for TXDSENT event */
13500 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
13502 /* Bit 2 : Write '1' to disable interrupt for RXDREADY event */
13507 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
13509 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
13514 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
13540 /* Bits 3..0 : Enable or disable TWI */
13543 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
13705 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
13711 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13717 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
13723 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
13729 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13735 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
13739 /* Description: Enable or disable interrupt */
13741 /* Bit 24 : Enable or disable interrupt for LASTTX event */
13744 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
13747 /* Bit 23 : Enable or disable interrupt for LASTRX event */
13750 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
13753 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
13756 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
13759 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
13762 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
13765 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
13768 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
13771 /* Bit 9 : Enable or disable interrupt for ERROR event */
13774 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
13777 /* Bit 1 : Enable or disable interrupt for STOPPED event */
13780 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
13836 /* Description: Disable interrupt */
13838 /* Bit 24 : Write '1' to disable interrupt for LASTTX event */
13843 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
13845 /* Bit 23 : Write '1' to disable interrupt for LASTRX event */
13850 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
13852 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
13857 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
13859 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
13864 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
13866 /* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */
13871 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
13873 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
13878 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13880 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
13885 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
13911 /* Bits 3..0 : Enable or disable TWIM */
13914 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
13988 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14018 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14115 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14121 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14125 /* Description: Enable or disable interrupt */
14127 /* Bit 26 : Enable or disable interrupt for READ event */
14130 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
14133 /* Bit 25 : Enable or disable interrupt for WRITE event */
14136 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
14139 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
14142 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
14145 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
14148 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
14151 /* Bit 9 : Enable or disable interrupt for ERROR event */
14154 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
14157 /* Bit 1 : Enable or disable interrupt for STOPPED event */
14160 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
14209 /* Description: Disable interrupt */
14211 /* Bit 26 : Write '1' to disable interrupt for READ event */
14216 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
14218 /* Bit 25 : Write '1' to disable interrupt for WRITE event */
14223 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
14225 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
14230 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
14232 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
14237 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
14239 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
14244 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14246 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
14251 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
14284 /* Bits 3..0 : Enable or disable TWIS */
14287 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
14376 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
14382 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
14482 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
14488 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
14537 /* Description: Disable interrupt */
14539 /* Bit 17 : Write '1' to disable interrupt for RXTO event */
14544 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
14546 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
14551 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14553 /* Bit 7 : Write '1' to disable interrupt for TXDRDY event */
14558 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
14560 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
14565 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
14567 /* Bit 1 : Write '1' to disable interrupt for NCTS event */
14572 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
14574 /* Bit 0 : Write '1' to disable interrupt for CTS event */
14579 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
14611 /* Bits 3..0 : Enable or disable UART */
14614 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
14861 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
14867 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
14871 /* Description: Enable or disable interrupt */
14873 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
14876 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
14879 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
14882 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
14885 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
14888 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
14891 /* Bit 17 : Enable or disable interrupt for RXTO event */
14894 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
14897 /* Bit 9 : Enable or disable interrupt for ERROR event */
14900 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
14903 /* Bit 8 : Enable or disable interrupt for ENDTX event */
14906 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
14909 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
14912 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
14915 /* Bit 4 : Enable or disable interrupt for ENDRX event */
14918 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
14921 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
14924 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
14927 /* Bit 1 : Enable or disable interrupt for NCTS event */
14930 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
14933 /* Bit 0 : Enable or disable interrupt for CTS event */
14936 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
15020 /* Description: Disable interrupt */
15022 /* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */
15027 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
15029 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
15034 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
15036 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
15041 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
15043 /* Bit 17 : Write '1' to disable interrupt for RXTO event */
15048 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
15050 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
15055 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
15057 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
15062 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
15064 /* Bit 7 : Write '1' to disable interrupt for TXDRDY event */
15069 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
15071 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
15076 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
15078 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
15083 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
15085 /* Bit 1 : Write '1' to disable interrupt for NCTS event */
15090 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
15092 /* Bit 0 : Write '1' to disable interrupt for CTS event */
15097 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
15129 /* Bits 3..0 : Enable or disable UARTE */
15132 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
15336 /* Bits 7..0 : Enable or disable access port protection. */
15340 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
15357 #define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB re…
15363 #define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */
15530 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
15536 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
15542 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
15548 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
15554 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
15558 /* Description: Enable or disable interrupt */
15560 /* Bit 24 : Enable or disable interrupt for EPDATA event */
15563 #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
15566 /* Bit 23 : Enable or disable interrupt for EP0SETUP event */
15569 #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
15572 /* Bit 22 : Enable or disable interrupt for USBEVENT event */
15575 #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
15578 /* Bit 21 : Enable or disable interrupt for SOF event */
15581 #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
15584 /* Bit 20 : Enable or disable interrupt for ENDISOOUT event */
15587 #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
15590 /* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */
15593 #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
15596 /* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */
15599 #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
15602 /* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */
15605 #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
15608 /* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */
15611 #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
15614 /* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */
15617 #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
15620 /* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */
15623 #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
15626 /* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */
15629 #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
15632 /* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */
15635 #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
15638 /* Bit 11 : Enable or disable interrupt for ENDISOIN event */
15641 #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
15644 /* Bit 10 : Enable or disable interrupt for EP0DATADONE event */
15647 #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
15650 /* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */
15653 #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
15656 /* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */
15659 #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
15662 /* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */
15665 #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
15668 /* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */
15671 #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
15674 /* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */
15677 #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
15680 /* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */
15683 #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
15686 /* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */
15689 #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
15692 /* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */
15695 #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
15698 /* Bit 1 : Enable or disable interrupt for STARTED event */
15701 #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
15704 /* Bit 0 : Enable or disable interrupt for USBRESET event */
15707 #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
15889 /* Description: Disable interrupt */
15891 /* Bit 24 : Write '1' to disable interrupt for EPDATA event */
15896 #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
15898 /* Bit 23 : Write '1' to disable interrupt for EP0SETUP event */
15903 #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
15905 /* Bit 22 : Write '1' to disable interrupt for USBEVENT event */
15910 #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
15912 /* Bit 21 : Write '1' to disable interrupt for SOF event */
15917 #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
15919 /* Bit 20 : Write '1' to disable interrupt for ENDISOOUT event */
15924 #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
15926 /* Bit 19 : Write '1' to disable interrupt for ENDEPOUT[7] event */
15931 #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
15933 /* Bit 18 : Write '1' to disable interrupt for ENDEPOUT[6] event */
15938 #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
15940 /* Bit 17 : Write '1' to disable interrupt for ENDEPOUT[5] event */
15945 #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
15947 /* Bit 16 : Write '1' to disable interrupt for ENDEPOUT[4] event */
15952 #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
15954 /* Bit 15 : Write '1' to disable interrupt for ENDEPOUT[3] event */
15959 #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
15961 /* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */
15966 #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
15968 /* Bit 13 : Write '1' to disable interrupt for ENDEPOUT[1] event */
15973 #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
15975 /* Bit 12 : Write '1' to disable interrupt for ENDEPOUT[0] event */
15980 #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
15982 /* Bit 11 : Write '1' to disable interrupt for ENDISOIN event */
15987 #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
15989 /* Bit 10 : Write '1' to disable interrupt for EP0DATADONE event */
15994 #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
15996 /* Bit 9 : Write '1' to disable interrupt for ENDEPIN[7] event */
16001 #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
16003 /* Bit 8 : Write '1' to disable interrupt for ENDEPIN[6] event */
16008 #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
16010 /* Bit 7 : Write '1' to disable interrupt for ENDEPIN[5] event */
16015 #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
16017 /* Bit 6 : Write '1' to disable interrupt for ENDEPIN[4] event */
16022 #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
16024 /* Bit 5 : Write '1' to disable interrupt for ENDEPIN[3] event */
16029 #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
16031 /* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */
16036 #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
16038 /* Bit 3 : Write '1' to disable interrupt for ENDEPIN[1] event */
16043 #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
16045 /* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */
16050 #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
16052 /* Bit 1 : Write '1' to disable interrupt for STARTED event */
16057 #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
16059 /* Bit 0 : Write '1' to disable interrupt for USBRESET event */
16064 #define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
16480 #define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */
16486 #define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
16492 #define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
16498 #define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
16504 #define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
16510 #define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
16516 #define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
16522 #define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
16528 #define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
16537 #define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */
16543 #define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
16549 #define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
16555 #define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
16561 #define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
16567 #define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
16573 #define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
16579 #define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
16585 #define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
16754 /* Description: Disable interrupt */
16756 /* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */
16761 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
16833 /* Bit 7 : Enable or disable RR[7] register */
16836 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
16839 /* Bit 6 : Enable or disable RR[6] register */
16842 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
16845 /* Bit 5 : Enable or disable RR[5] register */
16848 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
16851 /* Bit 4 : Enable or disable RR[4] register */
16854 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
16857 /* Bit 3 : Enable or disable RR[3] register */
16860 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
16863 /* Bit 2 : Enable or disable RR[2] register */
16866 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
16869 /* Bit 1 : Enable or disable RR[1] register */
16872 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
16875 /* Bit 0 : Enable or disable RR[0] register */
16878 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */