Lines Matching full:description

39 /* Description: Accelerated Address Resolver */
42 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
49 /* Description: Stop resolving addresses */
56 /* Description: Address resolution procedure complete */
63 /* Description: Address resolved */
70 /* Description: Address not resolved */
77 /* Description: Enable interrupt */
101 /* Description: Disable interrupt */
125 /* Description: Resolution status */
132 /* Description: Enable AAR */
141 /* Description: Number of IRKs */
148 /* Description: Pointer to IRK data structure */
155 /* Description: Pointer to the resolvable address */
162 /* Description: Pointer to data area used for temporary storage */
170 /* Description: Access control lists */
173 /* Description: Description cluster[n]: Configure the word-aligned start address of region n to pro…
180 /* Description: Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR…
187 /* Description: Description cluster[n]: Access permissions for region n as defined by start address…
203 /* Description: AES CCM Mode Encryption */
206 /* Description: Start generation of key-stream. This operation will stop by itself when completed. …
213 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
220 /* Description: Stop encryption/decryption */
227 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE re…
234 /* Description: Key-stream generation complete */
241 /* Description: Encrypt/decrypt complete */
248 /* Description: Deprecated register - CCM error event */
255 /* Description: Shortcut register */
264 /* Description: Enable interrupt */
288 /* Description: Disable interrupt */
312 /* Description: MIC check result */
321 /* Description: Enable */
330 /* Description: Operation mode */
353 /* Description: Pointer to data structure holding AES key and NONCE vector */
360 /* Description: Input pointer */
367 /* Description: Output pointer */
374 /* Description: Pointer to data area used for temporary storage */
382 /* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
389 /* Description: Data rate override setting. */
401 /* Description: CRYPTOCELL HOST_RGF interface */
404 /* Description: AES hardware key select */
414 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_…
423 /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the C…
430 /* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the …
437 /* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the …
444 /* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the…
451 /* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */
467 /* Description: Clock control */
470 /* Description: Start HFXO crystal oscillator */
477 /* Description: Stop HFXO crystal oscillator */
484 /* Description: Start LFCLK */
491 /* Description: Stop LFCLK */
498 /* Description: Start calibration of LFRC */
505 /* Description: Start calibration timer */
512 /* Description: Stop calibration timer */
519 /* Description: HFXO crystal oscillator started */
526 /* Description: LFCLK started */
533 /* Description: Calibration of LFRC completed */
540 /* Description: Calibration timer timeout */
547 /* Description: Calibration timer has been started and is ready to process new tasks */
554 /* Description: Calibration timer has been stopped and is ready to process new tasks */
561 /* Description: Enable interrupt */
606 /* Description: Disable interrupt */
651 /* Description: Status indicating that HFCLKSTART task has been triggered */
660 /* Description: HFCLK status */
675 /* Description: Status indicating that LFCLKSTART task has been triggered */
684 /* Description: LFCLK status */
700 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
710 /* Description: Clock source for the LFCLK */
732 /* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */
741 /* Description: Calibration timer interval */
748 /* Description: Clocking options for the trace port debug interface */
766 /* Description: LFRC mode configuration */
782 /* Description: Comparator */
785 /* Description: Start comparator */
792 /* Description: Stop comparator */
799 /* Description: Sample comparator value */
806 /* Description: COMP is ready and output is valid */
813 /* Description: Downward crossing */
820 /* Description: Upward crossing */
827 /* Description: Downward or upward crossing */
834 /* Description: Shortcut register */
867 /* Description: Enable or disable interrupt */
894 /* Description: Enable interrupt */
925 /* Description: Disable interrupt */
956 /* Description: Compare result */
965 /* Description: COMP enable */
974 /* Description: Pin select */
989 /* Description: Reference source select for single-ended mode */
1001 /* Description: External reference select */
1016 /* Description: Threshold configuration for hysteresis unit */
1027 /* Description: Mode configuration */
1043 /* Description: Comparator hysteresis enable */
1053 /* Description: ARM TrustZone CryptoCell register interface */
1056 /* Description: Enable CRYPTOCELL subsystem */
1066 /* Description: AES ECB Mode Encryption */
1069 /* Description: Start ECB block encrypt */
1076 /* Description: Abort a possible executing ECB operation */
1083 /* Description: ECB block encrypt complete */
1090 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1097 /* Description: Enable interrupt */
1114 /* Description: Disable interrupt */
1131 /* Description: ECB block encrypt memory pointers */
1139 /* Description: Event Generator Unit 0 */
1142 /* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] …
1149 /* Description: Description collection[n]: Event number n generated by triggering the corresponding…
1156 /* Description: Enable or disable interrupt */
1255 /* Description: Enable interrupt */
1370 /* Description: Disable interrupt */
1486 /* Description: Factory information configuration registers */
1489 /* Description: Code memory page size */
1496 /* Description: Code memory size */
1503 /* Description: Description collection[n]: Device identifier */
1510 /* Description: Description collection[n]: Encryption root, word n */
1517 /* Description: Description collection[n]: Identity Root, word n */
1524 /* Description: Device address type */
1533 /* Description: Description collection[n]: Device address n */
1540 /* Description: Part code */
1549 /* Description: Build code (hardware version and production configuration) */
1564 /* Description: Package option */
1573 /* Description: RAM variant */
1586 /* Description: Flash variant */
1599 /* Description: Description collection[n]: Production test signature n */
1608 /* Description: Slope definition A0 */
1615 /* Description: Slope definition A1 */
1622 /* Description: Slope definition A2 */
1629 /* Description: Slope definition A3 */
1636 /* Description: Slope definition A4 */
1643 /* Description: Slope definition A5 */
1650 /* Description: Y-intercept B0 */
1657 /* Description: Y-intercept B1 */
1664 /* Description: Y-intercept B2 */
1671 /* Description: Y-intercept B3 */
1678 /* Description: Y-intercept B4 */
1685 /* Description: Y-intercept B5 */
1692 /* Description: Segment end T0 */
1699 /* Description: Segment end T1 */
1706 /* Description: Segment end T2 */
1713 /* Description: Segment end T3 */
1720 /* Description: Segment end T4 */
1727 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1746 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1765 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1784 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1803 /* Description: Amount of bytes for the required entropy bits */
1810 /* Description: Repetition counter cutoff */
1817 /* Description: Adaptive proportion cutoff */
1824 /* Description: Amount of bytes for the startup tests */
1831 /* Description: Sample count for ring oscillator 1 */
1838 /* Description: Sample count for ring oscillator 2 */
1845 /* Description: Sample count for ring oscillator 3 */
1852 /* Description: Sample count for ring oscillator 4 */
1860 /* Description: GPIO Tasks and Events */
1863 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Act…
1870 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Act…
1877 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Act…
1884 /* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */
1891 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1898 /* Description: Enable interrupt */
1964 /* Description: Disable interrupt */
2030 /* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN…
2063 /* Description: Inter-IC Sound */
2066 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2073 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {…
2080 /* Description: The RXD.PTR register has been copied to internal double-buffers.
2088 /* Description: I2S transfer stopped. */
2095 /* Description: The TDX.PTR register has been copied to internal double-buffers.
2103 /* Description: Enable or disable interrupt */
2124 /* Description: Enable interrupt */
2148 /* Description: Disable interrupt */
2172 /* Description: Enable I2S module. */
2181 /* Description: I2S mode. */
2190 /* Description: Reception (RX) enable. */
2199 /* Description: Transmission (TX) enable. */
2208 /* Description: Master clock generator enable. */
2217 /* Description: Master clock generator frequency. */
2242 /* Description: MCK / LRCK ratio. */
2258 /* Description: Sample width. */
2268 /* Description: Alignment of sample within a frame. */
2277 /* Description: Frame format. */
2286 /* Description: Enable channels. */
2296 /* Description: Receive buffer RAM start address. */
2303 /* Description: Transmit buffer RAM start address. */
2310 /* Description: Size of RXD and TXD buffers. */
2317 /* Description: Pin select for MCK signal. */
2334 /* Description: Pin select for SCK signal. */
2351 /* Description: Pin select for LRCK signal. */
2368 /* Description: Pin select for SDIN signal. */
2385 /* Description: Pin select for SDOUT signal. */
2403 /* Description: Low Power Comparator */
2406 /* Description: Start comparator */
2413 /* Description: Stop comparator */
2420 /* Description: Sample comparator value */
2427 /* Description: LPCOMP is ready and output is valid */
2434 /* Description: Downward crossing */
2441 /* Description: Upward crossing */
2448 /* Description: Downward or upward crossing */
2455 /* Description: Shortcut register */
2488 /* Description: Enable interrupt */
2519 /* Description: Disable interrupt */
2550 /* Description: Compare result */
2559 /* Description: Enable LPCOMP */
2568 /* Description: Input pin select */
2583 /* Description: Reference select */
2606 /* Description: External reference select */
2615 /* Description: Analog detect configuration */
2625 /* Description: Comparator hysteresis enable */
2635 /* Description: Memory Watch Unit */
2638 /* Description: Description cluster[n]: Write access to region n detected */
2645 /* Description: Description cluster[n]: Read access to region n detected */
2652 /* Description: Description cluster[n]: Write access to peripheral region n detected */
2659 /* Description: Description cluster[n]: Read access to peripheral region n detected */
2666 /* Description: Enable or disable interrupt */
2741 /* Description: Enable interrupt */
2828 /* Description: Disable interrupt */
2915 /* Description: Enable or disable non-maskable interrupt */
2990 /* Description: Enable non-maskable interrupt */
3077 /* Description: Disable non-maskable interrupt */
3164 /* Description: Description cluster[n]: Source of event/interrupt in region n, write access detecte…
3359 /* Description: Description cluster[n]: Source of event/interrupt in region n, read access detected…
3554 /* Description: Enable/disable regions watch */
3629 /* Description: Enable regions watch */
3716 /* Description: Disable regions watch */
3803 /* Description: Description cluster[n]: Start address for region n */
3810 /* Description: Description cluster[n]: End address of region n */
3817 /* Description: Description cluster[n]: Reserved for future use */
3824 /* Description: Description cluster[n]: Reserved for future use */
3831 /* Description: Description cluster[n]: Subregions of region n */
4027 /* Description: NFC-A compatible radio */
4030 /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activate…
4037 /* Description: Disable NFCT peripheral */
4044 /* Description: Enable NFC sense field mode, change state to sense mode */
4051 /* Description: Start transmission of an outgoing frame, change state to transmit */
4058 /* Description: Initializes the EasyDMA for receive. */
4065 /* Description: Force state machine to IDLE state */
4072 /* Description: Force state machine to SLEEP_A state */
4079 /* Description: The NFCT peripheral is ready to receive and send frames */
4086 /* Description: Remote NFC field detected */
4093 /* Description: Remote NFC field lost */
4100 /* Description: Marks the start of the first symbol of a transmitted frame */
4107 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
4114 /* Description: Marks the end of the first symbol of a received frame */
4121 /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA ha…
4128 /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the …
4135 /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the so…
4142 /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4149 /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffe…
4156 /* Description: Auto collision resolution process has started */
4163 /* Description: NFC auto collision resolution error reported. */
4170 /* Description: NFC auto collision resolution successfully completed */
4177 /* Description: EasyDMA is ready to receive or send frames. */
4184 /* Description: Shortcut register */
4205 /* Description: Enable or disable interrupt */
4298 /* Description: Enable interrupt */
4406 /* Description: Disable interrupt */
4514 /* Description: NFC Error Status register */
4521 /* Description: Result of last incoming frame */
4542 /* Description: NfcTag state register */
4555 /* Description: Sleep state during automatic collision resolution */
4566 /* Description: Indicates the presence or not of a valid field */
4581 /* Description: Minimum frame delay */
4588 /* Description: Maximum frame delay */
4595 /* Description: Configuration register for the Frame Delay Timer */
4606 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
4613 /* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
4620 /* Description: Configuration of outgoing frames */
4647 /* Description: Size of outgoing frame */
4658 /* Description: Configuration of incoming frames */
4679 /* Description: Size of last incoming frame */
4690 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
4709 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
4724 /* Description: Third last NFCID1 part (10 bytes ID) */
4739 /* Description: Controls the auto collision resolution function. This setting must be done before t…
4748 /* Description: NFC-A SENS_RES auto-response settings */
4780 /* Description: NFC-A SEL_RES auto-response settings */
4804 /* Description: Non Volatile Memory Controller */
4807 /* Description: Ready flag */
4816 /* Description: Ready flag */
4825 /* Description: Configuration register */
4835 /* Description: Register for erasing a page in code area */
4842 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
4849 /* Description: Register for erasing all non-volatile user memory */
4858 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
4865 /* Description: Register for erasing user information configuration registers */
4874 /* Description: Register for partial erase of a page in code area */
4881 /* Description: Register for partial erase configuration */
4888 /* Description: I-code cache configuration register. */
4903 /* Description: I-code cache hit counter. */
4910 /* Description: I-code cache miss counter. */
4918 /* Description: GPIO Port 1 */
4921 /* Description: Write GPIO port */
5116 /* Description: Set individual bits in GPIO port */
5343 /* Description: Clear individual bits in GPIO port */
5570 /* Description: Read GPIO port */
5765 /* Description: Direction of GPIO pins */
5960 /* Description: DIR set register */
6187 /* Description: DIR clear register */
6414 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_…
6609 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
6618 /* Description: Description collection[n]: Configuration of GPIO pins */
6660 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
6663 /* Description: Starts continuous PDM transfer */
6670 /* Description: Stops PDM transfer */
6677 /* Description: PDM transfer has started */
6684 /* Description: PDM transfer has finished */
6691 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample …
6698 /* Description: Enable or disable interrupt */
6719 /* Description: Enable interrupt */
6743 /* Description: Disable interrupt */
6767 /* Description: PDM module enable register */
6776 /* Description: PDM clock generator control */
6789 /* Description: Defines the routing of the connected PDM microphones' signals */
6804 /* Description: Left output gain adjustment */
6814 /* Description: Right output gain adjustment */
6824 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordi…
6833 /* Description: Pin number configuration for PDM CLK signal */
6850 /* Description: Pin number configuration for PDM DIN signal */
6867 /* Description: RAM address pointer to write samples to with EasyDMA */
6874 /* Description: Number of samples to allocate memory for in EasyDMA mode */
6882 /* Description: Power control */
6885 /* Description: Enable constant latency mode */
6892 /* Description: Enable low power mode (variable latency) */
6899 /* Description: Power failure warning */
6906 /* Description: CPU entered WFI/WFE sleep */
6913 /* Description: CPU exited WFI/WFE sleep */
6920 /* Description: Voltage supply detected on VBUS */
6927 /* Description: Voltage supply removed from VBUS */
6934 /* Description: USB 3.3 V supply ready */
6941 /* Description: Enable interrupt */
6986 /* Description: Disable interrupt */
7031 /* Description: Reset reason */
7088 /* Description: Deprecated register - RAM status register */
7115 /* Description: USB supply status */
7130 /* Description: System OFF register */
7138 /* Description: Power-fail comparator configuration */
7183 /* Description: General purpose retention register */
7190 /* Description: General purpose retention register */
7197 /* Description: Enable DC/DC converter for REG1 stage. */
7206 /* Description: Enable DC/DC converter for REG0 stage. */
7215 /* Description: Main supply status */
7224 /* Description: Description cluster[n]: RAMn power control register */
7419 /* Description: Description cluster[n]: RAMn power control set register */
7582 /* Description: Description cluster[n]: RAMn power control clear register */
7746 /* Description: Programmable Peripheral Interconnect */
7749 /* Description: Description cluster[n]: Enable channel group n */
7756 /* Description: Description cluster[n]: Disable channel group n */
7763 /* Description: Channel enable register */
7958 /* Description: Channel enable set register */
8185 /* Description: Channel enable clear register */
8412 /* Description: Description cluster[n]: Channel n event end-point */
8419 /* Description: Description cluster[n]: Channel n task end-point */
8426 /* Description: Description collection[n]: Channel group n */
8621 /* Description: Description cluster[n]: Channel n task end-point */
8629 /* Description: Pulse width modulation unit 0 */
8632 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and st…
8639 /* Description: Description collection[n]: Loads the first PWM value on all enabled channels from s…
8646 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=…
8653 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
8660 /* Description: Description collection[n]: First PWM period started on sequence n */
8667 /* Description: Description collection[n]: Emitted at end of every sequence n, when last value from…
8674 /* Description: Emitted at the end of each PWM period */
8681 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
8688 /* Description: Shortcut register */
8721 /* Description: Enable or disable interrupt */
8766 /* Description: Enable interrupt */
8818 /* Description: Disable interrupt */
8870 /* Description: PWM module enable register */
8879 /* Description: Selects operating mode of the wave counter */
8888 /* Description: Value up to which the pulse generator counter counts */
8895 /* Description: Configuration for PWM_CLK */
8910 /* Description: Configuration of the decoder */
8927 /* Description: Number of playbacks of a loop */
8935 /* Description: Description cluster[n]: Beginning address in RAM of this sequence */
8942 /* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */
8950 /* Description: Description cluster[n]: Number of additional PWM periods between samples loaded int…
8958 /* Description: Description cluster[n]: Time added after the sequence */
8965 /* Description: Description collection[n]: Output pin select for PWM channel n */
8983 /* Description: Quadrature Decoder */
8986 /* Description: Task starting the quadrature decoder */
8993 /* Description: Task stopping the quadrature decoder */
9000 /* Description: Read and clear ACC and ACCDBL */
9007 /* Description: Read and clear ACC */
9014 /* Description: Read and clear ACCDBL */
9021 /* Description: Event being generated for every new sample value written to the SAMPLE register */
9028 /* Description: Non-null report ready */
9035 /* Description: ACC or ACCDBL register overflow */
9042 /* Description: Double displacement(s) detected */
9049 /* Description: QDEC has been stopped */
9056 /* Description: Shortcut register */
9101 /* Description: Enable interrupt */
9139 /* Description: Disable interrupt */
9177 /* Description: Enable the quadrature decoder */
9186 /* Description: LED output pin polarity */
9195 /* Description: Sample period */
9213 /* Description: Motion sample value */
9220 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
9236 /* Description: Register accumulating the valid transitions */
9243 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
9250 /* Description: Pin select for LED signal */
9267 /* Description: Pin select for A signal */
9284 /* Description: Pin select for B signal */
9301 /* Description: Enable input debounce filters */
9310 /* Description: Time period the LED is switched ON prior to sampling */
9317 /* Description: Register accumulating the number of detected double transitions */
9324 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
9332 /* Description: External flash interface */
9335 /* Description: Activate QSPI interface */
9342 /* Description: Start transfer from external flash memory to internal RAM */
9349 /* Description: Start transfer from internal RAM to external flash memory */
9356 /* Description: Start external flash memory erase operation */
9363 /* Description: Deactivate QSPI interface */
9370 /* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI ta…
9377 /* Description: Enable or disable interrupt */
9386 /* Description: Enable interrupt */
9396 /* Description: Disable interrupt */
9406 /* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */
9415 /* Description: Flash memory source address */
9422 /* Description: RAM destination address */
9429 /* Description: Read transfer length */
9436 /* Description: Flash destination address */
9443 /* Description: RAM source address */
9450 /* Description: Write transfer length */
9457 /* Description: Start address of flash block to be erased */
9464 /* Description: Size of block to be erased. */
9474 /* Description: Pin select for serial clock SCK */
9491 /* Description: Pin select for chip select signal CSN. */
9508 /* Description: Pin select for serial data MOSI/IO0. */
9525 /* Description: Pin select for serial data MISO/IO1. */
9542 /* Description: Pin select for serial data IO2. */
9559 /* Description: Pin select for serial data IO3. */
9576 /* Description: Address offset into the external memory for Execute in Place operation. */
9583 /* Description: Interface configuration. */
9621 /* Description: Interface configuration. */
9644 /* Description: Status register. */
9663 /* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
9674 /* Description: Extended address configuration. */
9709 /* Description: Custom instruction configuration register. */
9760 /* Description: Custom instruction data register 0. */
9779 /* Description: Custom instruction data register 1. */
9798 /* Description: SPI interface timing. */
9806 /* Description: 2.4 GHz radio */
9809 /* Description: Enable RADIO in TX mode */
9816 /* Description: Enable RADIO in RX mode */
9823 /* Description: Start RADIO */
9830 /* Description: Stop RADIO */
9837 /* Description: Disable RADIO */
9844 /* Description: Start the RSSI and take one single sample of the receive signal strength */
9851 /* Description: Stop the RSSI measurement */
9858 /* Description: Start the bit counter */
9865 /* Description: Stop the bit counter */
9872 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
9879 /* Description: Stop the energy detect measurement */
9886 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
9893 /* Description: Stop the clear channel assessment */
9900 /* Description: RADIO has ramped up and is ready to be started */
9907 /* Description: Address sent or received */
9914 /* Description: Packet payload sent or received */
9921 /* Description: Packet sent or received */
9928 /* Description: RADIO has been disabled */
9935 /* Description: A device address match occurred on the last received packet */
9942 /* Description: No device address match occurred on the last received packet */
9949 /* Description: Sampling of receive signal strength complete */
9956 /* Description: Bit counter reached bit count value */
9963 /* Description: Packet received with CRC ok */
9970 /* Description: Packet received with CRC error */
9977 /* Description: IEEE 802.15.4 length field received */
9984 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from th…
9991 /* Description: The sampling of energy detection has stopped */
9998 /* Description: Wireless medium in idle - clear to send */
10005 /* Description: Wireless medium busy - do not send */
10012 /* Description: The CCA has stopped */
10019 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kb…
10026 /* Description: RADIO has ramped up and is ready to be started TX path */
10033 /* Description: RADIO has ramped up and is ready to be started RX path */
10040 /* Description: MAC header match found */
10047 /* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last…
10054 /* Description: Shortcut register */
10171 /* Description: Enable interrupt */
10328 /* Description: Disable interrupt */
10485 /* Description: CRC status */
10494 /* Description: Received address */
10501 /* Description: CRC field of previously received packet */
10508 /* Description: Device address match index */
10515 /* Description: Payload status */
10530 /* Description: Packet pointer */
10537 /* Description: Frequency */
10550 /* Description: Output power */
10572 /* Description: Data rate and modulation */
10586 /* Description: Packet configuration register 0 */
10629 /* Description: Packet configuration register 1 */
10656 /* Description: Base address 0 */
10663 /* Description: Base address 1 */
10670 /* Description: Prefixes bytes for logical addresses 0-3 */
10689 /* Description: Prefixes bytes for logical addresses 4-7 */
10708 /* Description: Transmit address select */
10715 /* Description: Receive address select */
10766 /* Description: CRC configuration */
10784 /* Description: CRC polynomial */
10791 /* Description: CRC initial value */
10798 /* Description: Interframe spacing in us */
10805 /* Description: RSSI sample */
10812 /* Description: Current radio state */
10828 /* Description: Data whitening initial value */
10835 /* Description: Bit counter compare */
10842 /* Description: Description collection[n]: Device address base segment n */
10849 /* Description: Description collection[n]: Device address prefix n */
10856 /* Description: Device address match configuration */
10939 /* Description: Radio mode configuration register 0 */
10955 /* Description: IEEE 802.15.4 start of frame delimiter */
10962 /* Description: IEEE 802.15.4 energy detect loop count */
10969 /* Description: IEEE 802.15.4 energy detect level */
10976 /* Description: IEEE 802.15.4 clear channel assessment control */
11000 /* Description: Peripheral power control */
11010 /* Description: Random Number Generator */
11013 /* Description: Task starting the random number generator */
11020 /* Description: Task stopping the random number generator */
11027 /* Description: Event being generated for every new random number written to the VALUE register */
11034 /* Description: Shortcut register */
11043 /* Description: Enable interrupt */
11053 /* Description: Disable interrupt */
11063 /* Description: Configuration register */
11072 /* Description: Output random number */
11080 /* Description: Real time counter 0 */
11083 /* Description: Start RTC COUNTER */
11090 /* Description: Stop RTC COUNTER */
11097 /* Description: Clear RTC COUNTER */
11104 /* Description: Set COUNTER to 0xFFFFF0 */
11111 /* Description: Event on COUNTER increment */
11118 /* Description: Event on COUNTER overflow */
11125 /* Description: Description collection[n]: Compare event on CC[n] match */
11132 /* Description: Enable interrupt */
11177 /* Description: Disable interrupt */
11222 /* Description: Enable or disable event routing */
11261 /* Description: Enable event routing */
11306 /* Description: Disable event routing */
11351 /* Description: Current COUNTER value */
11358 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when R…
11365 /* Description: Description collection[n]: Compare register n */
11373 /* Description: Successive approximation register (SAR) analog-to-digital converter */
11376 /* Description: Starts the SAADC and prepares the result buffer in RAM */
11383 /* Description: Takes one SAADC sample */
11390 /* Description: Stops the SAADC and terminates all on-going conversions */
11397 /* Description: Starts offset auto-calibration */
11404 /* Description: The SAADC has started */
11411 /* Description: The SAADC has filled up the result buffer */
11418 /* Description: A conversion task has been completed. Depending on the configuration, multiple conv…
11425 /* Description: Result ready for transfer to RAM */
11432 /* Description: Calibration is complete */
11439 /* Description: The SAADC has stopped */
11446 /* Description: Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */
11453 /* Description: Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */
11460 /* Description: Enable or disable interrupt */
11595 /* Description: Enable interrupt */
11752 /* Description: Disable interrupt */
11909 /* Description: Status */
11918 /* Description: Enable or disable SAADC */
11927 /* Description: Description cluster[n]: Input positive pin selection for CH[n] */
11945 /* Description: Description cluster[n]: Input negative pin selection for CH[n] */
11963 /* Description: Description cluster[n]: Input configuration for CH[n] */
12022 /* Description: Description cluster[n]: High/low limits for event monitoring of a channel */
12033 /* Description: Resolution configuration */
12044 /* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for hi…
12060 /* Description: Controls normal or continuous sample rate */
12073 /* Description: Data pointer */
12080 /* Description: Maximum number of 16-bit samples to be written to output RAM buffer */
12087 /* Description: Number of 16-bit samples written to output RAM buffer since the previous START task…
12095 /* Description: Serial Peripheral Interface 0 */
12098 /* Description: TXD byte sent and RXD byte received */
12105 /* Description: Enable interrupt */
12115 /* Description: Disable interrupt */
12125 /* Description: Enable SPI */
12134 /* Description: Pin select for SCK */
12151 /* Description: Pin select for MOSI signal */
12168 /* Description: Pin select for MISO signal */
12185 /* Description: RXD register */
12192 /* Description: TXD register */
12199 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12213 /* Description: Configuration register */
12235 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
12238 /* Description: Start SPI transaction */
12245 /* Description: Stop SPI transaction */
12252 /* Description: Suspend SPI transaction */
12259 /* Description: Resume SPI transaction */
12266 /* Description: SPI transaction has stopped */
12273 /* Description: End of RXD buffer reached */
12280 /* Description: End of RXD buffer and TXD buffer reached */
12287 /* Description: End of TXD buffer reached */
12294 /* Description: Transaction started */
12301 /* Description: Shortcut register */
12310 /* Description: Enable interrupt */
12348 /* Description: Disable interrupt */
12386 /* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL …
12401 /* Description: Enable SPIM */
12410 /* Description: Pin select for SCK */
12427 /* Description: Pin select for MOSI signal */
12444 /* Description: Pin select for MISO signal */
12461 /* Description: Pin select for CSN */
12478 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12494 /* Description: Data pointer */
12501 /* Description: Maximum number of bytes in receive buffer */
12508 /* Description: Number of bytes transferred in the last transaction */
12515 /* Description: EasyDMA list type */
12524 /* Description: Data pointer */
12531 /* Description: Number of bytes in transmit buffer */
12538 /* Description: Number of bytes transferred in the last transaction */
12545 /* Description: EasyDMA list type */
12554 /* Description: Configuration register */
12575 /* Description: Sample delay for input serial data on MISO */
12582 /* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must …
12589 /* Description: Polarity of CSN output */
12598 /* Description: Pin select for DCX signal */
12615 /* Description: DCX configuration */
12622 /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.…
12630 /* Description: SPI Slave 0 */
12633 /* Description: Acquire SPI semaphore */
12640 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
12647 /* Description: Granted transaction completed */
12654 /* Description: End of RXD buffer reached */
12661 /* Description: Semaphore acquired */
12668 /* Description: Shortcut register */
12677 /* Description: Enable interrupt */
12701 /* Description: Disable interrupt */
12725 /* Description: Semaphore status register */
12736 /* Description: Status from last transaction */
12753 /* Description: Enable SPI slave */
12762 /* Description: Pin select for SCK */
12779 /* Description: Pin select for MISO signal */
12796 /* Description: Pin select for MOSI signal */
12813 /* Description: Pin select for CSN signal */
12830 /* Description: RXD data pointer */
12837 /* Description: Maximum number of bytes in receive buffer */
12844 /* Description: Number of bytes received in last granted transaction */
12851 /* Description: TXD data pointer */
12858 /* Description: Maximum number of bytes in transmit buffer */
12865 /* Description: Number of bytes transmitted in last granted transaction */
12872 /* Description: Configuration register */
12893 /* Description: Default character. Character clocked out in case of an ignored transaction. */
12900 /* Description: Over-read character */
12908 /* Description: Temperature Sensor */
12911 /* Description: Start temperature measurement */
12918 /* Description: Stop temperature measurement */
12925 /* Description: Temperature measurement complete, data ready */
12932 /* Description: Enable interrupt */
12942 /* Description: Disable interrupt */
12952 /* Description: Temperature in degC (0.25deg steps) */
12959 /* Description: Slope of 1st piece wise linear function */
12966 /* Description: Slope of 2nd piece wise linear function */
12973 /* Description: Slope of 3rd piece wise linear function */
12980 /* Description: Slope of 4th piece wise linear function */
12987 /* Description: Slope of 5th piece wise linear function */
12994 /* Description: Slope of 6th piece wise linear function */
13001 /* Description: y-intercept of 1st piece wise linear function */
13008 /* Description: y-intercept of 2nd piece wise linear function */
13015 /* Description: y-intercept of 3rd piece wise linear function */
13022 /* Description: y-intercept of 4th piece wise linear function */
13029 /* Description: y-intercept of 5th piece wise linear function */
13036 /* Description: y-intercept of 6th piece wise linear function */
13043 /* Description: End point of 1st piece wise linear function */
13050 /* Description: End point of 2nd piece wise linear function */
13057 /* Description: End point of 3rd piece wise linear function */
13064 /* Description: End point of 4th piece wise linear function */
13071 /* Description: End point of 5th piece wise linear function */
13079 /* Description: Timer/Counter 0 */
13082 /* Description: Start Timer */
13089 /* Description: Stop Timer */
13096 /* Description: Increment Timer (Counter mode only) */
13103 /* Description: Clear time */
13110 /* Description: Deprecated register - Shut down timer */
13117 /* Description: Description collection[n]: Capture Timer value to CC[n] register */
13124 /* Description: Description collection[n]: Compare event on CC[n] match */
13131 /* Description: Shortcut register */
13206 /* Description: Enable interrupt */
13251 /* Description: Disable interrupt */
13296 /* Description: Timer mode selection */
13306 /* Description: Configure the number of bits used by the TIMER */
13317 /* Description: Timer prescaler register */
13324 /* Description: Description collection[n]: Capture/Compare register n */
13332 /* Description: I2C compatible Two-Wire Interface 0 */
13335 /* Description: Start TWI receive sequence */
13342 /* Description: Start TWI transmit sequence */
13349 /* Description: Stop TWI transaction */
13356 /* Description: Suspend TWI transaction */
13363 /* Description: Resume TWI transaction */
13370 /* Description: TWI stopped */
13377 /* Description: TWI RXD byte received */
13384 /* Description: TWI TXD byte sent */
13391 /* Description: TWI error */
13398 /* Description: TWI byte boundary, generated before each byte that is sent or received */
13405 /* Description: TWI entered the suspended state */
13412 /* Description: Shortcut register */
13427 /* Description: Enable interrupt */
13472 /* Description: Disable interrupt */
13517 /* Description: Error source */
13538 /* Description: Enable TWI */
13547 /* Description: Pin select for SCL */
13564 /* Description: Pin select for SDA */
13581 /* Description: RXD register */
13588 /* Description: TXD register */
13595 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
13605 /* Description: Address used in the TWI transfer */
13613 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
13616 /* Description: Start TWI receive sequence */
13623 /* Description: Start TWI transmit sequence */
13630 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
13637 /* Description: Suspend TWI transaction */
13644 /* Description: Resume TWI transaction */
13651 /* Description: TWI stopped */
13658 /* Description: TWI error */
13665 /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is …
13672 /* Description: Receive sequence started */
13679 /* Description: Transmit sequence started */
13686 /* Description: Byte boundary, starting to receive the last byte */
13693 /* Description: Byte boundary, starting to transmit the last byte */
13700 /* Description: Shortcut register */
13739 /* Description: Enable or disable interrupt */
13784 /* Description: Enable interrupt */
13836 /* Description: Disable interrupt */
13888 /* Description: Error source */
13909 /* Description: Enable TWIM */
13918 /* Description: Pin select for SCL signal */
13935 /* Description: Pin select for SDA signal */
13952 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
13962 /* Description: Data pointer */
13969 /* Description: Maximum number of bytes in receive buffer */
13976 /* Description: Number of bytes transferred in the last transaction */
13983 /* Description: EasyDMA list type */
13992 /* Description: Data pointer */
13999 /* Description: Maximum number of bytes in transmit buffer */
14006 /* Description: Number of bytes transferred in the last transaction */
14013 /* Description: EasyDMA list type */
14022 /* Description: Address used in the TWI transfer */
14030 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
14033 /* Description: Stop TWI transaction */
14040 /* Description: Suspend TWI transaction */
14047 /* Description: Resume TWI transaction */
14054 /* Description: Prepare the TWI slave to respond to a write command */
14061 /* Description: Prepare the TWI slave to respond to a read command */
14068 /* Description: TWI stopped */
14075 /* Description: TWI error */
14082 /* Description: Receive sequence started */
14089 /* Description: Transmit sequence started */
14096 /* Description: Write command received */
14103 /* Description: Read command received */
14110 /* Description: Shortcut register */
14125 /* Description: Enable or disable interrupt */
14164 /* Description: Enable interrupt */
14209 /* Description: Disable interrupt */
14254 /* Description: Error source */
14275 /* Description: Status register indicating which address had a match */
14282 /* Description: Enable TWIS */
14291 /* Description: Pin select for SCL signal */
14308 /* Description: Pin select for SDA signal */
14325 /* Description: RXD Data pointer */
14332 /* Description: Maximum number of bytes in RXD buffer */
14339 /* Description: Number of bytes transferred in the last RXD transaction */
14346 /* Description: TXD Data pointer */
14353 /* Description: Maximum number of bytes in TXD buffer */
14360 /* Description: Number of bytes transferred in the last TXD transaction */
14367 /* Description: Description collection[n]: TWI slave address n */
14374 /* Description: Configuration register for the address match mechanism */
14389 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
14397 /* Description: Universal Asynchronous Receiver/Transmitter */
14400 /* Description: Start UART receiver */
14407 /* Description: Stop UART receiver */
14414 /* Description: Start UART transmitter */
14421 /* Description: Stop UART transmitter */
14428 /* Description: Suspend UART */
14435 /* Description: CTS is activated (set low). Clear To Send. */
14442 /* Description: CTS is deactivated (set high). Not Clear To Send. */
14449 /* Description: Data received in RXD */
14456 /* Description: Data sent from TXD */
14463 /* Description: Error detected */
14470 /* Description: Receiver timeout */
14477 /* Description: Shortcut register */
14492 /* Description: Enable interrupt */
14537 /* Description: Disable interrupt */
14582 /* Description: Error source */
14609 /* Description: Enable UART */
14618 /* Description: Pin select for RTS */
14635 /* Description: Pin select for TXD */
14652 /* Description: Pin select for CTS */
14669 /* Description: Pin select for RXD */
14686 /* Description: RXD register */
14693 /* Description: TXD register */
14700 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
14725 /* Description: Configuration of parity and hardware flow control */
14741 /* Description: UART with EasyDMA 0 */
14744 /* Description: Start UART receiver */
14751 /* Description: Stop UART receiver */
14758 /* Description: Start UART transmitter */
14765 /* Description: Stop UART transmitter */
14772 /* Description: Flush RX FIFO into RX buffer */
14779 /* Description: CTS is activated (set low). Clear To Send. */
14786 /* Description: CTS is deactivated (set high). Not Clear To Send. */
14793 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
14800 /* Description: Receive buffer is filled up */
14807 /* Description: Data sent from TXD */
14814 /* Description: Last TX byte transmitted */
14821 /* Description: Error detected */
14828 /* Description: Receiver timeout */
14835 /* Description: UART receiver has started */
14842 /* Description: UART transmitter has started */
14849 /* Description: Transmitter stopped */
14856 /* Description: Shortcut register */
14871 /* Description: Enable or disable interrupt */
14940 /* Description: Enable interrupt */
15020 /* Description: Disable interrupt */
15100 /* Description: Error source Note : this register is read / write one to clear. */
15127 /* Description: Enable UART */
15136 /* Description: Pin select for RTS signal */
15153 /* Description: Pin select for TXD signal */
15170 /* Description: Pin select for CTS signal */
15187 /* Description: Pin select for RXD signal */
15204 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
15229 /* Description: Data pointer */
15236 /* Description: Maximum number of bytes in receive buffer */
15243 /* Description: Number of bytes transferred in the last transaction */
15250 /* Description: Data pointer */
15257 /* Description: Maximum number of bytes in transmit buffer */
15264 /* Description: Number of bytes transferred in the last transaction */
15271 /* Description: Configuration of parity and hardware flow control */
15293 /* Description: User information configuration registers */
15296 /* Description: Description collection[n]: Reserved for Nordic firmware design */
15303 /* Description: Description collection[n]: Reserved for Nordic hardware design */
15310 /* Description: Description collection[n]: Reserved for customer */
15317 /* Description: Description collection[n]: Mapping of the nRESET function */
15334 /* Description: Access port protection */
15343 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
15352 /* Description: Processor debug control */
15367 /* Description: GPIO reference voltage / external output supply voltage in high voltage mode */
15382 /* Description: Universal serial bus device */
15385 /* Description: Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers va…
15392 /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data …
15399 /* Description: Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers …
15406 /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving o…
15413 /* Description: Allows OUT data stage on control endpoint 0 */
15420 /* Description: Allows status stage on control endpoint 0 */
15427 /* Description: Stalls data and status stage on control endpoint 0 */
15434 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
15441 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
15448 /* Description: Signals that a USB reset condition has been detected on USB lines */
15455 /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXC…
15462 /* Description: Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buff…
15469 /* Description: An acknowledged data transfer has taken place on the control endpoint */
15476 /* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by …
15483 /* Description: Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buf…
15490 /* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by…
15497 /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */
15504 /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE …
15511 /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */
15518 /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS regi…
15525 /* Description: Shortcut register */
15558 /* Description: Enable or disable interrupt */
15711 /* Description: Enable interrupt */
15889 /* Description: Disable interrupt */
16067 /* Description: Details on what caused the USBEVENT event */
16100 /* Description: Description collection[n]: IN endpoint halted status. Can be used as is as response…
16109 /* Description: Description collection[n]: OUT endpoint halted status. Can be used as is as respons…
16118 /* Description: Provides information on which endpoint's EasyDMA registers have been captured */
16229 /* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurre…
16316 /* Description: Device USB address */
16323 /* Description: SETUP data, byte 0, bmRequestType */
16347 /* Description: SETUP data, byte 1, bRequest */
16365 /* Description: SETUP data, byte 2, LSB of wValue */
16372 /* Description: SETUP data, byte 3, MSB of wValue */
16379 /* Description: SETUP data, byte 4, LSB of wIndex */
16386 /* Description: SETUP data, byte 5, MSB of wIndex */
16393 /* Description: SETUP data, byte 6, LSB of wLength */
16400 /* Description: SETUP data, byte 7, MSB of wLength */
16407 /* Description: Description collection[n]: Number of bytes received last in the data stage of this …
16414 /* Description: Number of bytes received last on this ISO OUT data endpoint */
16427 /* Description: Enable USB */
16436 /* Description: Control of the USB pull-up */
16445 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE ta…
16455 /* Description: Data toggle control and status */
16475 /* Description: Endpoint IN enable */
16532 /* Description: Endpoint OUT enable */
16589 /* Description: STALL endpoints */
16608 /* Description: Controls the split of ISO buffers */
16617 /* Description: Returns the current value of the start of frame counter */
16624 /* Description: Controls USBD peripheral low power mode during USB suspend */
16633 /* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready t…
16642 /* Description: Description cluster[n]: Data pointer */
16649 /* Description: Description cluster[n]: Maximum number of bytes to transfer */
16656 /* Description: Description cluster[n]: Number of bytes transferred in the last transaction */
16663 /* Description: Data pointer */
16670 /* Description: Maximum number of bytes to transfer */
16677 /* Description: Number of bytes transferred in the last transaction */
16684 /* Description: Description cluster[n]: Data pointer */
16691 /* Description: Description cluster[n]: Maximum number of bytes to transfer */
16698 /* Description: Description cluster[n]: Number of bytes transferred in the last transaction */
16705 /* Description: Data pointer */
16712 /* Description: Maximum number of bytes to transfer */
16719 /* Description: Number of bytes transferred in the last transaction */
16727 /* Description: Watchdog Timer */
16730 /* Description: Start the watchdog */
16737 /* Description: Watchdog timeout */
16744 /* Description: Enable interrupt */
16754 /* Description: Disable interrupt */
16764 /* Description: Run status */
16773 /* Description: Request status */
16824 /* Description: Counter reload value */
16831 /* Description: Enable register for reload request registers */
16882 /* Description: Configuration register */
16897 /* Description: Description collection[n]: Reload request n */