Lines Matching full:read

82 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
83 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
89 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
90 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
96 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
97 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
106 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
107 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
113 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
114 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
120 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
121 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
189 /* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */
190 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
191 #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
192 #define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */
193 #define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */
269 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
270 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
276 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
277 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
283 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
284 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
293 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
294 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
300 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
301 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
307 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
308 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
425 … : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the C…
453 /* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured…
566 #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
567 #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
573 #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
574 #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
580 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
581 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
587 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
588 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
594 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
595 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
601 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
602 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
611 #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
612 #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
618 #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
619 #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
625 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
626 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
632 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
633 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
639 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
640 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
646 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
647 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
768 /* Bit 16 : Active LFRC mode. This field is read only. */
899 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
900 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
906 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
907 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
913 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
914 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
920 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
921 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
930 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
931 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
937 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
938 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
944 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
945 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
951 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
952 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1102 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1103 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1109 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1110 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1119 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1120 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1126 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1127 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1260 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1261 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1267 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1268 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1274 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1275 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1281 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1282 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1288 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1289 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1295 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1296 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1302 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1303 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1309 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1310 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1316 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1317 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1323 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1324 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1330 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1331 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1337 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1338 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1344 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1345 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1351 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1352 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1358 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1359 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1365 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1366 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1375 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1376 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1382 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1383 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1389 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1390 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1396 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1397 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1403 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1404 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1410 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1411 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1417 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1418 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1424 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1425 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1431 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1432 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1438 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1439 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1445 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1446 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1452 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1453 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1459 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1460 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1466 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1467 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1473 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1474 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1480 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1481 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1727 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1746 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1765 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1784 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_L…
1903 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1904 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1910 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1911 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1917 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1918 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1924 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1925 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1931 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1932 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1938 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1939 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1945 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1946 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1952 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1953 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1959 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1960 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1969 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1970 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1976 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1977 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1983 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1984 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1990 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1991 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1997 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1998 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2004 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2005 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2011 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2012 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2018 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2019 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2025 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2026 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2129 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2130 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2136 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2137 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2143 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2144 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2153 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2154 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2160 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2161 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2167 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2168 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2204 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read fr…
2493 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2494 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2500 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2501 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2507 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2508 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2514 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2515 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2524 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2525 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2531 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2532 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2538 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2539 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2545 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2546 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2645 /* Description: Description cluster[n]: Read access to region n detected */
2659 /* Description: Description cluster[n]: Read access to peripheral region n detected */
2746 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2747 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2753 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2754 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2760 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2761 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2767 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2768 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2774 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2775 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2781 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2782 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2788 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2789 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2795 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2796 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2802 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2803 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2809 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2810 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2816 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2817 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2823 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2824 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2833 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2834 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2840 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2841 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2847 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2848 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2854 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2855 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2861 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2862 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2868 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2869 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2875 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2876 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2882 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2883 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2889 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2890 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2896 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2897 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2903 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2904 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2910 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2911 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2995 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2996 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3002 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3003 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3009 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3010 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3016 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3017 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3023 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3024 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3030 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3031 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3037 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3038 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3044 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3045 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3051 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3052 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3058 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3059 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3065 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3066 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3072 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3073 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3082 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3083 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3089 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3090 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3096 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3097 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3103 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3104 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3110 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3111 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3117 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3118 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3124 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3125 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3131 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3132 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3138 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3139 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3145 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3146 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3152 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3153 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3159 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3160 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3359 /* Description: Description cluster[n]: Source of event/interrupt in region n, read access detected…
3364 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion …
3365 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3370 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion …
3371 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3376 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion …
3377 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3382 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion …
3383 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3388 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion …
3389 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3394 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion …
3395 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3400 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion …
3401 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3406 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion …
3407 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3412 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion …
3413 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3418 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion …
3419 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3424 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion …
3425 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3430 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion …
3431 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3436 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion …
3437 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3442 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion …
3443 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3448 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion …
3449 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3454 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion …
3455 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3460 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion …
3461 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3466 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion …
3467 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3472 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion …
3473 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3478 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion …
3479 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3484 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion …
3485 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3490 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion …
3491 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3496 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
3497 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3502 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
3503 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3508 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
3509 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3514 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
3515 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3520 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
3521 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3526 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
3527 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3532 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
3533 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3538 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
3539 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3544 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
3545 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3550 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
3551 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3556 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3559 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3560 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3568 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3571 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3572 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3580 /* Bit 7 : Enable/disable read access watch in region[3] */
3583 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3584 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3592 /* Bit 5 : Enable/disable read access watch in region[2] */
3595 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3596 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3604 /* Bit 3 : Enable/disable read access watch in region[1] */
3607 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3608 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3616 /* Bit 1 : Enable/disable read access watch in region[0] */
3619 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3620 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3631 /* Bit 27 : Enable read access watch in PREGION[1] */
3634 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3635 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3636 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3645 /* Bit 25 : Enable read access watch in PREGION[0] */
3648 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3649 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3650 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3659 /* Bit 7 : Enable read access watch in region[3] */
3662 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3663 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3664 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3673 /* Bit 5 : Enable read access watch in region[2] */
3676 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3677 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3678 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3687 /* Bit 3 : Enable read access watch in region[1] */
3690 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3691 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3692 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3701 /* Bit 1 : Enable read access watch in region[0] */
3704 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3705 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3706 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3718 /* Bit 27 : Disable read access watch in PREGION[1] */
3721 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3722 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3723 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3732 /* Bit 25 : Disable read access watch in PREGION[0] */
3735 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3736 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3737 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3746 /* Bit 7 : Disable read access watch in region[3] */
3749 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3750 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3751 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3760 /* Bit 5 : Disable read access watch in region[2] */
3763 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3764 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3765 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3774 /* Bit 3 : Disable read access watch in region[1] */
3777 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3778 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3779 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3788 /* Bit 1 : Disable read access watch in region[0] */
3791 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3792 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3793 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
4303 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4304 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4310 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4311 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4317 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4318 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4324 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4325 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4331 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4332 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4338 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4339 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4345 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4346 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4352 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4353 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4359 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4360 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4366 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4367 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4373 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4374 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4380 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4381 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4387 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4388 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4394 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4395 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4401 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4402 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4411 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4412 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4418 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4419 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4425 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4426 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4432 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4433 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4439 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4440 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4446 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4447 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4453 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4454 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4460 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4461 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4467 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4468 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4474 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4475 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4481 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4482 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4488 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4489 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4495 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4496 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4502 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4503 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4509 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4510 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4626 …TX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is us…
4653 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the…
4830 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
5121 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5122 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5128 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5129 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5135 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5136 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5142 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5143 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5149 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5150 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5156 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5157 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5163 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5164 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5170 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5171 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5177 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5178 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5184 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5185 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5191 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5192 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5198 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5199 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5205 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5206 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5212 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5213 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5219 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5220 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5226 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5227 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5233 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5234 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5240 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5241 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5247 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5248 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5254 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5255 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5261 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5262 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5268 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5269 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5275 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5276 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5282 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5283 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5289 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5290 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5296 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5297 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5303 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5304 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5310 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5311 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5317 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5318 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5324 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5325 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5331 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5332 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5338 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5339 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5348 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5349 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5355 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5356 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5362 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5363 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5369 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5370 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5376 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5377 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5383 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
5384 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5390 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
5391 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5397 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
5398 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5404 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
5405 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5411 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
5412 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5418 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
5419 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5425 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
5426 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5432 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
5433 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5439 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
5440 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5446 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
5447 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5453 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
5454 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5460 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
5461 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5467 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
5468 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5474 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
5475 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5481 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
5482 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5488 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
5489 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5495 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
5496 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5502 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
5503 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5509 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
5510 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5516 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
5517 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5523 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
5524 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5530 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
5531 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5537 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
5538 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5544 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
5545 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5551 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
5552 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5558 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
5559 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5565 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
5566 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5570 /* Description: Read GPIO port */
5965 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
5966 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
5972 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
5973 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
5979 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
5980 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
5986 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
5987 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
5993 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
5994 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
6000 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
6001 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
6007 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
6008 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
6014 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
6015 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
6021 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
6022 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
6028 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
6029 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
6035 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
6036 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
6042 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
6043 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
6049 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
6050 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
6056 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
6057 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
6063 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
6064 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
6070 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
6071 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
6077 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
6078 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
6084 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
6085 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6091 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6092 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6098 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6099 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6105 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6106 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6112 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6113 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6119 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6120 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6126 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6127 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6133 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6134 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6140 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6141 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6147 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6148 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6154 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6155 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6161 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6162 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6168 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6169 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6175 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6176 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6182 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6183 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6192 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6193 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6199 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6200 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6206 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6207 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6213 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6214 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6220 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6221 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6227 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6228 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6234 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6235 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6241 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6242 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6248 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6249 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6255 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6256 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6262 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6263 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6269 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6270 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6276 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6277 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6283 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6284 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6290 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6291 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6297 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6298 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6304 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6305 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6311 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6312 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6318 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6319 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6325 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6326 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6332 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6333 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6339 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6340 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6346 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6347 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6353 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6354 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6360 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6361 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6367 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6368 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6374 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6375 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6381 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6382 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6388 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
6389 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6395 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
6396 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6402 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
6403 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6409 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
6410 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6724 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6725 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6731 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6732 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6738 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6739 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6748 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6749 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6755 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6756 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6762 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6763 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6946 #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
6947 #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
6953 #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
6954 #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
6960 #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
6961 #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
6967 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6968 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6974 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6975 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6981 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6982 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6991 #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
6992 #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
6998 #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
6999 #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
7005 #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
7006 #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
7012 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7013 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7019 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7020 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7026 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7027 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7963 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
7964 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7970 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
7971 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7977 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
7978 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7984 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
7985 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7991 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
7992 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7998 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
7999 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
8005 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
8006 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
8012 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
8013 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
8019 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
8020 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
8026 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
8027 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
8033 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
8034 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
8040 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
8041 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
8047 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
8048 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
8054 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
8055 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
8061 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
8062 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
8068 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
8069 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
8075 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
8076 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
8082 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
8083 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
8089 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
8090 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
8096 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
8097 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
8103 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
8104 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
8110 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
8111 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
8117 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
8118 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
8124 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
8125 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
8131 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
8132 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
8138 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
8139 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
8145 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
8146 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
8152 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
8153 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
8159 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
8160 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
8166 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
8167 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
8173 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
8174 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
8180 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
8181 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
8190 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
8191 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
8197 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
8198 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
8204 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
8205 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
8211 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
8212 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
8218 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
8219 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
8225 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
8226 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
8232 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
8233 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
8239 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
8240 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
8246 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
8247 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
8253 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
8254 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
8260 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
8261 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
8267 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
8268 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
8274 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
8275 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
8281 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
8282 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
8288 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
8289 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
8295 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
8296 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
8302 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
8303 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
8309 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
8310 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
8316 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
8317 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
8323 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
8324 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
8330 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
8331 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
8337 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
8338 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
8344 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
8345 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
8351 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
8352 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
8358 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
8359 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
8365 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
8366 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
8372 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
8373 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
8379 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
8380 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
8386 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
8387 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
8393 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
8394 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
8400 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
8401 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
8407 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
8408 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
8771 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8772 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8778 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8779 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8785 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8786 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8792 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8793 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8799 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8800 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8806 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8807 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8813 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8814 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8823 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8824 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8830 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8831 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8837 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8838 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8844 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8845 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8851 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8852 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8858 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8859 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8865 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8866 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8918 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
9000 /* Description: Read and clear ACC and ACCDBL */
9007 /* Description: Read and clear ACC */
9014 /* Description: Read and clear ACCDBL */
9106 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9107 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9113 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9114 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9120 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9121 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9127 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9128 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9134 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9135 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9144 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9145 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9151 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9152 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9158 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9159 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9165 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9166 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9172 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9173 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9238 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPL…
9391 #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
9392 #define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
9401 #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
9402 #define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
9429 /* Description: Read transfer length */
9431 /* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. …
10176 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
10177 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
10183 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
10184 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
10190 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
10191 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
10197 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
10198 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
10204 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
10205 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
10211 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
10212 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
10218 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
10219 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
10225 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
10226 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
10232 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10233 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10239 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
10240 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
10246 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
10247 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
10253 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
10254 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
10260 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
10261 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
10267 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
10268 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
10274 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
10275 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
10281 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
10282 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
10288 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
10289 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
10295 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
10296 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
10302 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10303 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10309 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10310 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10316 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10317 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10323 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10324 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10333 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
10334 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
10340 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
10341 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
10347 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
10348 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
10354 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
10355 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
10361 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
10362 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
10368 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
10369 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
10375 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
10376 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
10382 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
10383 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
10389 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10390 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10396 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
10397 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
10403 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
10404 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
10410 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
10411 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
10417 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
10418 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
10424 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
10425 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
10431 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
10432 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
10438 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
10439 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
10445 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
10446 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
10452 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
10453 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
10459 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10460 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10466 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10467 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10473 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10474 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10480 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10481 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10830 …hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by th…
11048 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11049 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11058 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11059 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11137 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11138 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11144 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11145 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11151 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11152 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11158 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11159 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11165 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11166 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11172 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11173 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11182 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11183 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11189 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11190 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11196 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11197 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11203 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11204 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11210 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11211 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11217 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11218 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11266 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11267 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11273 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11274 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11280 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11281 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11287 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11288 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11294 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11295 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11301 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11302 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11311 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11312 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11318 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11319 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11325 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11326 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11332 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11333 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11339 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11340 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11346 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11347 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11600 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11601 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11607 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11608 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11614 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11615 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11621 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11622 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11628 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11629 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11635 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11636 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11642 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11643 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11649 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11650 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11656 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11657 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11663 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11664 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11670 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11671 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11677 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11678 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11684 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11685 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11691 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11692 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11698 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11699 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11705 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11706 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11712 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11713 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11719 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11720 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11726 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11727 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11733 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
11734 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
11740 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
11741 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
11747 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
11748 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
11757 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11758 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11764 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11765 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11771 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11772 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11778 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11779 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11785 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11786 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11792 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11793 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11799 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11800 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11806 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11807 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11813 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11814 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11820 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11821 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11827 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11828 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11834 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11835 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11841 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11842 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11848 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11849 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11855 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11856 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11862 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11863 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11869 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11870 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11876 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11877 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11883 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11884 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11890 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
11891 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
11897 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
11898 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
11904 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
11905 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12089 … to output RAM buffer since the previous START task. This register can be read after an END or STO…
12110 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
12111 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
12120 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
12121 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
12315 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
12316 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
12322 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12323 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12329 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12330 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12336 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12337 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12343 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12344 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12353 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
12354 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12360 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12361 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12367 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12368 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12374 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12375 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12381 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12382 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12682 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12683 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12689 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12690 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12696 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12697 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12706 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12707 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12713 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12714 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12720 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12721 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12741 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
12742 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
12745 /* Bit 0 : TX buffer over-read detected, and prevented */
12748 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
12749 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
12900 /* Description: Over-read character */
12902 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
12937 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
12938 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
12947 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
12948 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
13211 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13212 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13218 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13219 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13225 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13226 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13232 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13233 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13239 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13240 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13246 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13247 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13256 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13257 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13263 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13264 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13270 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13271 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13277 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13278 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13284 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13285 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13291 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13292 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13432 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13433 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13439 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
13440 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
13446 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13447 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13453 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13454 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13460 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13461 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13467 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13468 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13477 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13478 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13484 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
13485 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
13491 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13492 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13498 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13499 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13505 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13506 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13512 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13513 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13522 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
13523 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
13528 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
13529 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
13534 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
13535 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
13789 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
13790 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
13796 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13797 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13803 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13804 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13810 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13811 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13817 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13818 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13824 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13825 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13831 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13832 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13841 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
13842 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
13848 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13849 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13855 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13856 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13862 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13863 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13869 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13870 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13876 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13877 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13883 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13884 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14061 /* Description: Prepare the TWI slave to respond to a read command */
14103 /* Description: Read command received */
14112 /* Bit 14 : Shortcut between READ event and SUSPEND task */
14127 /* Bit 26 : Enable or disable interrupt for READ event */
14128 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
14129 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
14166 /* Bit 26 : Write '1' to enable interrupt for READ event */
14167 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
14168 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
14169 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
14170 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
14176 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
14177 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
14183 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14184 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14190 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14191 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14197 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14198 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14204 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14205 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14211 /* Bit 26 : Write '1' to disable interrupt for READ event */
14212 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
14213 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
14214 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
14215 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
14221 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
14222 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
14228 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14229 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14235 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14236 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14242 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14243 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14249 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14250 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14256 /* Bit 3 : TX buffer over-read detected, and prevented */
14389 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
14391 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
14497 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
14498 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
14504 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14505 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14511 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14512 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14518 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14519 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14525 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
14526 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
14532 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
14533 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
14542 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
14543 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
14549 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14550 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14556 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14557 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14563 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14564 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14570 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
14571 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
14577 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
14578 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
14587 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
14588 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
14593 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
14594 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
14599 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
14600 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
14605 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
14606 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
14945 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
14946 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
14952 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14953 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14959 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14960 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14966 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
14967 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
14973 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14974 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14980 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
14981 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
14987 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14988 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14994 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
14995 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15001 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15002 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15008 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
15009 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
15015 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
15016 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
15025 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
15026 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
15032 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15033 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15039 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15040 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15046 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
15047 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
15053 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
15054 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
15060 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
15061 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
15067 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
15068 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15074 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
15075 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15081 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15082 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15088 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
15089 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
15095 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
15096 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
15100 /* Description: Error source Note : this register is read / write one to clear. */
15105 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
15106 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
15111 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
15112 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
15117 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
15118 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
15123 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
15124 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
15716 #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
15717 #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
15723 #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
15724 #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
15730 #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
15731 #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
15737 #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
15738 #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
15744 #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
15745 #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
15751 #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
15752 #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
15758 #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
15759 #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
15765 #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
15766 #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
15772 #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
15773 #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
15779 #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
15780 #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
15786 #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
15787 #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
15793 #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
15794 #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
15800 #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
15801 #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
15807 #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
15808 #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
15814 #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
15815 #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
15821 #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
15822 #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
15828 #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
15829 #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
15835 #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
15836 #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
15842 #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
15843 #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
15849 #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
15850 #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
15856 #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
15857 #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
15863 #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
15864 #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
15870 #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
15871 #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
15877 #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
15878 #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
15884 #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
15885 #define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
15894 #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
15895 #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
15901 #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
15902 #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
15908 #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
15909 #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
15915 #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
15916 #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
15922 #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
15923 #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
15929 #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
15930 #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
15936 #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
15937 #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
15943 #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
15944 #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
15950 #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
15951 #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
15957 #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
15958 #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
15964 #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
15965 #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
15971 #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
15972 #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
15978 #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
15979 #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
15985 #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
15986 #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
15992 #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
15993 #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
15999 #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
16000 #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
16006 #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
16007 #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
16013 #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
16014 #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
16020 #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
16021 #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
16027 #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
16028 #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
16034 #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
16035 #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
16041 #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
16042 #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
16048 #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
16049 #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
16055 #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
16056 #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
16062 #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
16063 #define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
16749 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
16750 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
16759 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
16760 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */