Lines Matching full:write

79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
86 /* Bit 1 : Write '1' to enable interrupt for RESOLVED event */
93 /* Bit 0 : Write '1' to enable interrupt for END event */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
110 /* Bit 1 : Write '1' to disable interrupt for RESOLVED event */
117 /* Bit 0 : Write '1' to disable interrupt for END event */
175 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
181 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
187 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
193 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
199 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
205 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
211 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
217 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
223 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
229 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
235 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
241 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
247 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
253 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
259 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
265 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
271 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
277 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
283 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
289 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
295 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
301 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
307 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
313 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
319 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
325 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
331 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
337 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
343 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
349 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
355 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
361 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
370 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
376 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
382 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
388 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
394 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
400 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
406 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
412 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
418 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
424 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
430 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
436 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
442 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
448 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
454 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
460 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
540 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
547 /* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */
554 /* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */
564 /* Bit 2 : Write '1' to disable interrupt for ERROR event */
571 /* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */
578 /* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */
757 /* Bit 4 : Write '1' to enable interrupt for CTTO event */
764 /* Bit 3 : Write '1' to enable interrupt for DONE event */
771 /* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */
778 /* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */
788 /* Bit 4 : Write '1' to disable interrupt for CTTO event */
795 /* Bit 3 : Write '1' to disable interrupt for DONE event */
802 /* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */
809 /* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */
1020 /* Bit 3 : Write '1' to enable interrupt for CROSS event */
1027 /* Bit 2 : Write '1' to enable interrupt for UP event */
1034 /* Bit 1 : Write '1' to enable interrupt for DOWN event */
1041 /* Bit 0 : Write '1' to enable interrupt for READY event */
1051 /* Bit 3 : Write '1' to disable interrupt for CROSS event */
1058 /* Bit 2 : Write '1' to disable interrupt for UP event */
1065 /* Bit 1 : Write '1' to disable interrupt for DOWN event */
1072 /* Bit 0 : Write '1' to disable interrupt for READY event */
1210 /* Bit 1 : Write '1' to enable interrupt for ERRORECB event */
1217 /* Bit 0 : Write '1' to enable interrupt for ENDECB event */
1227 /* Bit 1 : Write '1' to disable interrupt for ERRORECB event */
1234 /* Bit 0 : Write '1' to disable interrupt for ENDECB event */
1368 /* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */
1375 /* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */
1382 /* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */
1389 /* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */
1396 /* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */
1403 /* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */
1410 /* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */
1417 /* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */
1424 /* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */
1431 /* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */
1438 /* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */
1445 /* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */
1452 /* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */
1459 /* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */
1466 /* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */
1473 /* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */
1483 /* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */
1490 /* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */
1497 /* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */
1504 /* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */
1511 /* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */
1518 /* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */
1525 /* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */
1532 /* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */
1539 /* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */
1546 /* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */
1553 /* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */
1560 /* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */
1567 /* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */
1574 /* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */
1581 /* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */
1588 /* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */
1864 /* Bit 31 : Write '1' to enable interrupt for PORT event */
1871 /* Bit 7 : Write '1' to enable interrupt for IN[7] event */
1878 /* Bit 6 : Write '1' to enable interrupt for IN[6] event */
1885 /* Bit 5 : Write '1' to enable interrupt for IN[5] event */
1892 /* Bit 4 : Write '1' to enable interrupt for IN[4] event */
1899 /* Bit 3 : Write '1' to enable interrupt for IN[3] event */
1906 /* Bit 2 : Write '1' to enable interrupt for IN[2] event */
1913 /* Bit 1 : Write '1' to enable interrupt for IN[1] event */
1920 /* Bit 0 : Write '1' to enable interrupt for IN[0] event */
1930 /* Bit 31 : Write '1' to disable interrupt for PORT event */
1937 /* Bit 7 : Write '1' to disable interrupt for IN[7] event */
1944 /* Bit 6 : Write '1' to disable interrupt for IN[6] event */
1951 /* Bit 5 : Write '1' to disable interrupt for IN[5] event */
1958 /* Bit 4 : Write '1' to disable interrupt for IN[4] event */
1965 /* Bit 3 : Write '1' to disable interrupt for IN[3] event */
1972 /* Bit 2 : Write '1' to disable interrupt for IN[2] event */
1979 /* Bit 1 : Write '1' to disable interrupt for IN[1] event */
1986 /* Bit 0 : Write '1' to disable interrupt for IN[0] event */
2031 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */
2037 /* Bits 1..0 : Program memory access mode. It is strongly recommended to activate erase and write m…
2041 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2102 /* Description: Write GPIO port */
2304 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2311 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2318 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2325 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2332 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2339 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2346 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2353 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2360 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2367 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2374 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2381 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2388 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2395 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2402 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2409 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2416 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2423 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2430 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2437 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2444 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2451 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2458 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2465 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2472 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2479 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2486 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2493 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2500 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2507 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2514 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2521 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
2531 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2538 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2545 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2552 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2559 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2566 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2573 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2580 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2587 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2594 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2601 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2608 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2615 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2622 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2629 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2636 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2643 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2650 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2657 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2664 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2671 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2678 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
2685 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2692 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2699 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2706 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2713 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2720 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2727 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2734 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2741 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
2748 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3148 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3155 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3162 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3169 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3176 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3183 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3190 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3197 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3204 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3211 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3218 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3225 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3232 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3239 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3246 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3253 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3260 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3267 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3274 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3281 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3288 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3295 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3302 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3309 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3316 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3323 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3330 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3337 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3344 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3351 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3358 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3365 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3375 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3382 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3389 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3396 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3403 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3410 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3417 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3424 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3431 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3438 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3445 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3452 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3459 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3466 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3473 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3480 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3487 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3494 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3501 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3508 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3515 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3522 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3529 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3536 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3543 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3550 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3557 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3564 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3571 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3578 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3585 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3592 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
3597 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to …
3603 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to …
3609 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to …
3615 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to …
3621 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to …
3627 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to …
3633 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to …
3639 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to …
3645 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to …
3651 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to …
3657 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to …
3663 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to …
3669 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to …
3675 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to …
3681 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to …
3687 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to …
3693 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to …
3699 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to …
3705 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to …
3711 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to …
3717 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to …
3723 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to …
3729 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to cle…
3735 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to cle…
3741 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to cle…
3747 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to cle…
3753 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to cle…
3759 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to cle…
3765 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to cle…
3771 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
3777 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to cle…
3783 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to cle…
3902 /* Bit 2 : Write '1' to enable interrupt for END event */
3909 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
3916 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
3926 /* Bit 2 : Write '1' to disable interrupt for END event */
3933 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
3940 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
4028 /* Description: RAM address pointer to write samples to with EasyDMA */
4030 /* Bits 31..0 : Address to write PDM samples to over DMA */
4083 /* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */
4090 /* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */
4097 /* Bit 2 : Write '1' to enable interrupt for POFWARN event */
4107 /* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */
4114 /* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */
4121 /* Bit 2 : Write '1' to disable interrupt for POFWARN event */
4517 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
4524 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
4531 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
4538 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
4545 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
4552 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
4559 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
4566 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
4573 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
4580 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
4587 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
4594 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
4601 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
4608 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
4615 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
4622 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
4629 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
4636 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
4643 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
4650 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
4657 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
4664 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
4671 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
4678 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
4685 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
4692 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
4699 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
4706 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
4713 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
4720 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
4727 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
4734 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
4744 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
4751 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
4758 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
4765 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
4772 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
4779 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
4786 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
4793 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
4800 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
4807 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
4814 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
4821 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
4828 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
4835 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
4842 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
4849 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
4856 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
4863 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
4870 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
4877 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
4884 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
4891 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
4898 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
4905 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
4912 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
4919 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
4926 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
4933 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
4940 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
4947 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
4954 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
4961 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
5320 /* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */
5327 /* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */
5334 /* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */
5341 /* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */
5348 /* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */
5355 /* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */
5362 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
5372 /* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */
5379 /* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */
5386 /* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */
5393 /* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */
5400 /* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */
5407 /* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */
5414 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
5651 /* Bit 4 : Write '1' to enable interrupt for STOPPED event */
5658 /* Bit 3 : Write '1' to enable interrupt for DBLRDY event */
5665 /* Bit 2 : Write '1' to enable interrupt for ACCOF event */
5672 /* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */
5679 /* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */
5689 /* Bit 4 : Write '1' to disable interrupt for STOPPED event */
5696 /* Bit 3 : Write '1' to disable interrupt for DBLRDY event */
5703 /* Bit 2 : Write '1' to disable interrupt for ACCOF event */
5710 /* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */
5717 /* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */
6064 /* Bit 13 : Write '1' to enable interrupt for CRCERROR event */
6071 /* Bit 12 : Write '1' to enable interrupt for CRCOK event */
6078 /* Bit 10 : Write '1' to enable interrupt for BCMATCH event */
6085 /* Bit 7 : Write '1' to enable interrupt for RSSIEND event */
6092 /* Bit 6 : Write '1' to enable interrupt for DEVMISS event */
6099 /* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */
6106 /* Bit 4 : Write '1' to enable interrupt for DISABLED event */
6113 /* Bit 3 : Write '1' to enable interrupt for END event */
6120 /* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */
6127 /* Bit 1 : Write '1' to enable interrupt for ADDRESS event */
6134 /* Bit 0 : Write '1' to enable interrupt for READY event */
6144 /* Bit 13 : Write '1' to disable interrupt for CRCERROR event */
6151 /* Bit 12 : Write '1' to disable interrupt for CRCOK event */
6158 /* Bit 10 : Write '1' to disable interrupt for BCMATCH event */
6165 /* Bit 7 : Write '1' to disable interrupt for RSSIEND event */
6172 /* Bit 6 : Write '1' to disable interrupt for DEVMISS event */
6179 /* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */
6186 /* Bit 4 : Write '1' to disable interrupt for DISABLED event */
6193 /* Bit 3 : Write '1' to disable interrupt for END event */
6200 /* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */
6207 /* Bit 1 : Write '1' to disable interrupt for ADDRESS event */
6214 /* Bit 0 : Write '1' to disable interrupt for READY event */
6697 /* Bit 0 : Write '1' to enable interrupt for VALRDY event */
6707 /* Bit 0 : Write '1' to disable interrupt for VALRDY event */
6786 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
6793 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
6800 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
6807 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
6814 /* Bit 1 : Write '1' to enable interrupt for OVRFLW event */
6821 /* Bit 0 : Write '1' to enable interrupt for TICK event */
6831 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
6838 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
6845 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
6852 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
6859 /* Bit 1 : Write '1' to disable interrupt for OVRFLW event */
6866 /* Bit 0 : Write '1' to disable interrupt for TICK event */
6915 /* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */
6922 /* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */
6929 /* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */
6936 /* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */
6943 /* Bit 1 : Write '1' to enable event routing for OVRFLW event */
6950 /* Bit 0 : Write '1' to enable event routing for TICK event */
6960 /* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */
6967 /* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */
6974 /* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */
6981 /* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */
6988 /* Bit 1 : Write '1' to disable event routing for OVRFLW event */
6995 /* Bit 0 : Write '1' to disable event routing for TICK event */
7249 /* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */
7256 /* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */
7263 /* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */
7270 /* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */
7277 /* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */
7284 /* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */
7291 /* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */
7298 /* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */
7305 /* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */
7312 /* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */
7319 /* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */
7326 /* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */
7333 /* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */
7340 /* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */
7347 /* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */
7354 /* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */
7361 /* Bit 5 : Write '1' to enable interrupt for STOPPED event */
7368 /* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */
7375 /* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */
7382 /* Bit 2 : Write '1' to enable interrupt for DONE event */
7389 /* Bit 1 : Write '1' to enable interrupt for END event */
7396 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
7406 /* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */
7413 /* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */
7420 /* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */
7427 /* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */
7434 /* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */
7441 /* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */
7448 /* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */
7455 /* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */
7462 /* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */
7469 /* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */
7476 /* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */
7483 /* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */
7490 /* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */
7497 /* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */
7504 /* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */
7511 /* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */
7518 /* Bit 5 : Write '1' to disable interrupt for STOPPED event */
7525 /* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */
7532 /* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */
7539 /* Bit 2 : Write '1' to disable interrupt for DONE event */
7546 /* Bit 1 : Write '1' to disable interrupt for END event */
7553 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
7822 /* Bit 19 : Write '1' to enable interrupt for STARTED event */
7829 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
7836 /* Bit 6 : Write '1' to enable interrupt for END event */
7843 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
7850 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
7860 /* Bit 19 : Write '1' to disable interrupt for STARTED event */
7867 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
7874 /* Bit 6 : Write '1' to disable interrupt for END event */
7881 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
7888 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
8096 /* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */
8103 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
8110 /* Bit 1 : Write '1' to enable interrupt for END event */
8120 /* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */
8127 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
8134 /* Bit 1 : Write '1' to disable interrupt for END event */
8160 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
8167 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
8335 /* Bit 0 : Write '1' to enable interrupt for DATARDY event */
8345 /* Bit 0 : Write '1' to disable interrupt for DATARDY event */
8609 /* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */
8616 /* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */
8623 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
8630 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
8637 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
8644 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
8654 /* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */
8661 /* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */
8668 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
8675 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
8682 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
8689 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
8906 /* Bit 24 : Write '1' to enable interrupt for LASTTX event */
8913 /* Bit 23 : Write '1' to enable interrupt for LASTRX event */
8920 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
8927 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
8934 /* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */
8941 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
8948 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
8958 /* Bit 24 : Write '1' to disable interrupt for LASTTX event */
8965 /* Bit 23 : Write '1' to disable interrupt for LASTRX event */
8972 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
8979 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
8986 /* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */
8993 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
9000 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
9010 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9016 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
9166 /* Description: Prepare the TWI slave to respond to a write command */
9208 /* Description: Write command received */
9230 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
9245 /* Bit 25 : Enable or disable interrupt for WRITE event */
9246 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9247 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
9278 /* Bit 26 : Write '1' to enable interrupt for READ event */
9285 /* Bit 25 : Write '1' to enable interrupt for WRITE event */
9286 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9287 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
9292 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
9299 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
9306 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
9313 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
9323 /* Bit 26 : Write '1' to disable interrupt for READ event */
9330 /* Bit 25 : Write '1' to disable interrupt for WRITE event */
9331 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9332 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
9337 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
9344 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
9351 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
9358 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
9702 /* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */
9709 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
9716 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
9723 /* Bit 17 : Write '1' to enable interrupt for RXTO event */
9730 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
9737 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
9744 /* Bit 7 : Write '1' to enable interrupt for TXDRDY event */
9751 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
9758 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
9765 /* Bit 1 : Write '1' to enable interrupt for NCTS event */
9772 /* Bit 0 : Write '1' to enable interrupt for CTS event */
9782 /* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */
9789 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
9796 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
9803 /* Bit 17 : Write '1' to disable interrupt for RXTO event */
9810 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
9817 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
9824 /* Bit 7 : Write '1' to disable interrupt for TXDRDY event */
9831 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
9838 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
9845 /* Bit 1 : Write '1' to disable interrupt for NCTS event */
9852 /* Bit 0 : Write '1' to disable interrupt for CTS event */
9860 /* Description: Error source Note : this register is read / write one to clear. */
10103 /* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */
10113 /* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */