Lines Matching full:read

82 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
83 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
89 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
90 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
96 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
97 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
106 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
107 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
113 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
114 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
120 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
121 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
543 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
544 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
550 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
551 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
557 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
558 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
567 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
568 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
574 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
575 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
581 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
582 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
760 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
761 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
767 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
768 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
774 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
775 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
781 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
782 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
791 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
792 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
798 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
799 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
805 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
806 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
812 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
813 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1023 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1024 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1030 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1031 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1037 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1038 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1044 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1045 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1054 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1055 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1061 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1062 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1068 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1069 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1075 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1076 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1213 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1214 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1220 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1221 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1230 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1231 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1237 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1238 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1371 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1372 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1378 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1379 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1385 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1386 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1392 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1393 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1399 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1400 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1406 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1407 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1413 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1414 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1420 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1421 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1427 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1428 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1434 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1435 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1441 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1442 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1448 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1449 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1455 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1456 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1462 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1463 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1469 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1470 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1476 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1477 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1486 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1487 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1493 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1494 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1500 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1501 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1507 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1508 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1514 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1515 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1521 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1522 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1528 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1529 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1535 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1536 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1542 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1543 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1549 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1550 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1556 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1557 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1563 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1564 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1570 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1571 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1577 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1578 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1584 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1585 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1591 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1592 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1867 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1868 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1874 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1875 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1881 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1882 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1888 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1889 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1895 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1896 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1902 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1903 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1909 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1910 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1916 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1917 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1923 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1924 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1933 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1934 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1940 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1941 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1947 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1948 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1954 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1955 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1961 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1962 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1968 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1969 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1975 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1976 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1982 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1983 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1989 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
1990 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2040 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
2302 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
2303 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2309 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
2310 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2316 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
2317 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2323 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
2324 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2330 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
2331 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2337 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
2338 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2344 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
2345 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2351 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
2352 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
2358 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
2359 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
2365 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
2366 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
2372 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
2373 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
2379 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
2380 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
2386 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
2387 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
2393 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
2394 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
2400 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
2401 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
2407 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
2408 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
2414 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
2415 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
2421 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
2422 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
2428 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
2429 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
2435 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
2436 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
2442 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
2443 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
2449 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
2450 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
2456 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
2457 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
2463 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
2464 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
2470 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
2471 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
2477 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
2478 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
2484 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
2485 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
2491 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
2492 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
2498 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
2499 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
2505 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
2506 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
2512 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
2513 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
2519 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
2520 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
2529 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
2530 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
2536 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
2537 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
2543 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
2544 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
2550 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
2551 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
2557 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
2558 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
2564 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
2565 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
2571 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
2572 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
2578 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
2579 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
2585 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
2586 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
2592 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
2593 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
2599 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
2600 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
2606 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
2607 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
2613 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
2614 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
2620 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
2621 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
2627 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
2628 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
2634 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
2635 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
2641 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
2642 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
2648 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
2649 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
2655 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
2656 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
2662 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
2663 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
2669 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
2670 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
2676 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
2677 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
2683 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
2684 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
2690 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
2691 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
2697 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
2698 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
2704 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
2705 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
2711 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
2712 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
2718 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
2719 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
2725 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
2726 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
2732 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
2733 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
2739 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
2740 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
2746 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
2747 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
2751 /* Description: Read GPIO port */
3146 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
3147 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
3153 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
3154 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
3160 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
3161 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
3167 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
3168 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
3174 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
3175 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
3181 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
3182 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
3188 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
3189 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
3195 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
3196 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
3202 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
3203 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
3209 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
3210 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
3216 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
3217 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
3223 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
3224 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
3230 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
3231 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
3237 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
3238 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
3244 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
3245 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
3251 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
3252 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
3258 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
3259 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
3265 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
3266 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
3272 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
3273 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
3279 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
3280 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
3286 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
3287 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
3293 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
3294 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
3300 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
3301 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
3307 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
3308 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
3314 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
3315 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
3321 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
3322 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
3328 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
3329 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
3335 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
3336 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
3342 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
3343 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
3349 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
3350 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
3356 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
3357 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
3363 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
3364 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
3373 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
3374 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
3380 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
3381 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
3387 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
3388 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
3394 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
3395 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
3401 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
3402 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
3408 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
3409 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
3415 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
3416 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
3422 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
3423 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
3429 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
3430 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
3436 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
3437 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
3443 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
3444 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
3450 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
3451 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
3457 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
3458 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
3464 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
3465 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
3471 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
3472 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
3478 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
3479 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
3485 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
3486 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
3492 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
3493 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
3499 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
3500 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
3506 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
3507 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
3513 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
3514 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
3520 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
3521 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
3527 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
3528 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
3534 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
3535 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
3541 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
3542 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
3548 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
3549 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
3555 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
3556 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
3562 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
3563 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
3569 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
3570 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
3576 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
3577 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
3583 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
3584 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
3590 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
3591 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
3905 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
3906 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
3912 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
3913 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
3919 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
3920 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
3929 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
3930 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
3936 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
3937 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
3943 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
3944 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4086 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4087 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4093 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4094 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4100 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4101 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4110 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4111 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4117 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4118 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4124 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4125 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4515 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
4516 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
4522 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
4523 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
4529 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
4530 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
4536 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
4537 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
4543 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
4544 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
4550 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
4551 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
4557 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
4558 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
4564 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
4565 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
4571 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
4572 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
4578 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
4579 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
4585 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
4586 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
4592 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
4593 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
4599 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
4600 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
4606 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
4607 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
4613 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
4614 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
4620 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
4621 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
4627 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
4628 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
4634 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
4635 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
4641 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
4642 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
4648 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
4649 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
4655 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
4656 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
4662 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
4663 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
4669 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
4670 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
4676 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
4677 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
4683 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
4684 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
4690 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
4691 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
4697 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
4698 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
4704 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
4705 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
4711 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
4712 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
4718 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
4719 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
4725 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
4726 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
4732 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
4733 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
4742 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
4743 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
4749 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
4750 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
4756 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
4757 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
4763 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
4764 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
4770 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
4771 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
4777 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
4778 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
4784 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
4785 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
4791 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
4792 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
4798 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
4799 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
4805 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
4806 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
4812 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
4813 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
4819 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
4820 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
4826 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
4827 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
4833 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
4834 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
4840 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
4841 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
4847 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
4848 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
4854 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
4855 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
4861 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
4862 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
4868 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
4869 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
4875 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
4876 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
4882 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
4883 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
4889 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
4890 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
4896 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
4897 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
4903 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
4904 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
4910 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
4911 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
4917 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
4918 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
4924 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
4925 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
4931 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
4932 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
4938 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
4939 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
4945 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
4946 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
4952 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
4953 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
4959 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
4960 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
5323 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5324 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5330 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5331 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5337 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5338 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5344 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5345 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5351 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5352 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5358 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5359 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5365 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5366 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5375 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5376 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5382 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5383 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5389 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5390 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5396 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5397 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5403 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5404 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5410 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5411 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5417 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5418 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5470 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
5548 /* Description: Read and clear ACC and ACCDBL */
5555 /* Description: Read and clear ACC */
5562 /* Description: Read and clear ACCDBL */
5654 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5655 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5661 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5662 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5668 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5669 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5675 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5676 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5682 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5683 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5692 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5693 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5699 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5700 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5706 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5707 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5713 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5714 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5720 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5721 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5786 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPL…
6067 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
6068 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
6074 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
6075 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
6081 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
6082 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
6088 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
6089 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
6095 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
6096 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
6102 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
6103 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
6109 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
6110 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
6116 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6117 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6123 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
6124 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
6130 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
6131 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
6137 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
6138 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
6147 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
6148 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
6154 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
6155 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
6161 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
6162 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
6168 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
6169 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
6175 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
6176 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
6182 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
6183 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
6189 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
6190 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
6196 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6197 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6203 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
6204 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
6210 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
6211 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
6217 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
6218 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
6527 …hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by th…
6700 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6701 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6710 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6711 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6789 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6790 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6796 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6797 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6803 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6804 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6810 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6811 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6817 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6818 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6824 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
6825 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
6834 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6835 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6841 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6842 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6848 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6849 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6855 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6856 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6862 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6863 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6869 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
6870 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
6918 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6919 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6925 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6926 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6932 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6933 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6939 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6940 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6946 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6947 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6953 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
6954 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
6963 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6964 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6970 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6971 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6977 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6978 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6984 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6985 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6991 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6992 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6998 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
6999 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
7252 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
7253 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
7259 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
7260 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
7266 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
7267 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
7273 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
7274 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
7280 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
7281 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
7287 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
7288 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
7294 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
7295 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
7301 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
7302 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
7308 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
7309 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
7315 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
7316 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
7322 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
7323 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
7329 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
7330 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
7336 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
7337 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
7343 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
7344 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
7350 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
7351 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
7357 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
7358 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
7364 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7365 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7371 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
7372 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
7378 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
7379 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
7385 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
7386 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
7392 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7393 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7399 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7400 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7409 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
7410 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
7416 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
7417 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
7423 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
7424 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
7430 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
7431 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
7437 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
7438 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
7444 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
7445 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
7451 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
7452 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
7458 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
7459 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
7465 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
7466 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
7472 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
7473 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
7479 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
7480 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
7486 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
7487 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
7493 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
7494 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
7500 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
7501 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
7507 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
7508 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
7514 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
7515 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
7521 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7522 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7528 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
7529 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
7535 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
7536 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
7542 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
7543 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
7549 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7550 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7556 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7557 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7739 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read afte…
7825 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7826 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7832 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7833 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7839 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7840 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7846 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7847 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7853 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7854 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7863 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7864 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7870 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7871 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7877 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7878 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7884 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7885 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7891 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7892 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8039 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer.…
8041 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. …
8099 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
8100 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
8106 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8107 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8113 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8114 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8123 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
8124 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
8130 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8131 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8137 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8138 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8158 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
8159 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
8162 /* Bit 0 : TX buffer over-read detected, and prevented */
8165 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
8166 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
8301 /* Description: Over-read character */
8303 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
8338 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8339 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8348 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8349 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8612 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8613 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8619 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8620 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8626 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8627 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8633 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8634 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8640 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8641 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8647 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8648 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8657 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8658 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8664 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8665 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8671 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8672 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8678 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8679 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8685 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8686 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8692 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8693 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8909 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8910 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8916 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8917 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8923 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8924 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8930 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8931 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8937 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
8938 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
8944 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
8945 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
8951 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8952 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8961 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8962 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8968 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8969 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8975 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8976 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8982 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8983 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8989 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
8990 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
8996 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
8997 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9003 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9004 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9173 /* Description: Prepare the TWI slave to respond to a read command */
9215 /* Description: Read command received */
9224 /* Bit 14 : Shortcut between READ event and SUSPEND task */
9239 /* Bit 26 : Enable or disable interrupt for READ event */
9240 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
9241 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
9278 /* Bit 26 : Write '1' to enable interrupt for READ event */
9279 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
9280 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
9281 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9282 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9288 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9289 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9295 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9296 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9302 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9303 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9309 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9310 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9316 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9317 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9323 /* Bit 26 : Write '1' to disable interrupt for READ event */
9324 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
9325 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
9326 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
9327 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9333 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
9334 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9340 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9341 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9347 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9348 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9354 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9355 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9361 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9362 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9368 /* Bit 3 : TX buffer over-read detected, and prevented */
9493 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
9495 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
9705 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
9706 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
9712 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9713 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9719 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9720 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9726 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
9727 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
9733 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9734 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9740 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
9741 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
9747 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
9748 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
9754 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9755 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9761 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
9762 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
9768 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
9769 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
9775 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
9776 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
9785 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
9786 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
9792 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9793 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9799 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9800 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9806 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
9807 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
9813 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9814 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9820 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
9821 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
9827 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
9828 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
9834 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9835 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9841 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
9842 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
9848 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
9849 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
9855 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
9856 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
9860 /* Description: Error source Note : this register is read / write one to clear. */
9865 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
9866 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
9871 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
9872 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
9877 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
9878 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
9883 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
9884 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10106 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10107 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10116 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10117 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */