Lines Matching full:enable

77 /* Description: Enable interrupt */
79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */
84 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
86 /* Bit 1 : Write '1' to enable interrupt for RESOLVED event */
91 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
93 /* Bit 0 : Write '1' to enable interrupt for END event */
98 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
132 /* Description: Enable AAR */
134 /* Bits 1..0 : Enable or disable AAR */
135 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
136 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
138 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
175 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
181 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
187 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
193 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
199 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
205 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
211 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
217 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
223 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
229 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
235 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
241 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
247 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
253 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
259 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
265 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
271 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
277 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
283 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
289 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
295 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
301 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
307 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
313 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
319 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
325 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
331 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
337 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
343 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
349 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
355 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
361 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
370 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
376 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
382 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
388 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
394 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
400 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
406 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
412 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
418 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
424 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
430 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
436 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
442 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
448 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
454 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
460 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
535 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
538 /* Description: Enable interrupt */
540 /* Bit 2 : Write '1' to enable interrupt for ERROR event */
545 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
547 /* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */
552 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
554 /* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */
559 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
595 /* Description: Enable */
597 /* Bits 1..0 : Enable or disable CCM */
598 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
599 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
601 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
755 /* Description: Enable interrupt */
757 /* Bit 4 : Write '1' to enable interrupt for CTTO event */
762 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
764 /* Bit 3 : Write '1' to enable interrupt for DONE event */
769 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
771 /* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */
776 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
778 /* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */
783 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
878 /* Bit 17 : Enable or disable external source for LFCLK */
882 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (S…
884 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
888 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
964 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
970 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
976 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
982 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
988 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
991 /* Description: Enable or disable interrupt */
993 /* Bit 3 : Enable or disable interrupt for CROSS event */
997 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
999 /* Bit 2 : Enable or disable interrupt for UP event */
1003 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1005 /* Bit 1 : Enable or disable interrupt for DOWN event */
1009 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1011 /* Bit 0 : Enable or disable interrupt for READY event */
1015 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1018 /* Description: Enable interrupt */
1020 /* Bit 3 : Write '1' to enable interrupt for CROSS event */
1025 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1027 /* Bit 2 : Write '1' to enable interrupt for UP event */
1032 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1034 /* Bit 1 : Write '1' to enable interrupt for DOWN event */
1039 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1041 /* Bit 0 : Write '1' to enable interrupt for READY event */
1046 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1089 /* Description: COMP enable */
1091 /* Bits 1..0 : Enable or disable COMP */
1092 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1093 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1095 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1167 /* Description: Comparator hysteresis enable */
1208 /* Description: Enable interrupt */
1210 /* Bit 1 : Write '1' to enable interrupt for ERRORECB event */
1215 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1217 /* Bit 0 : Write '1' to enable interrupt for ENDECB event */
1222 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1267 /* Description: Enable or disable interrupt */
1269 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1273 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1275 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1279 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1281 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1285 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1287 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1291 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1293 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1297 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1299 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1303 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1305 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1309 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1311 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1315 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1317 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1321 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1323 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1327 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1329 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1333 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1335 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1339 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1341 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1345 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1347 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1351 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1353 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1357 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1359 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1363 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1366 /* Description: Enable interrupt */
1368 /* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */
1373 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1375 /* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */
1380 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1382 /* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */
1387 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1389 /* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */
1394 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1396 /* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */
1401 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1403 /* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */
1408 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1410 /* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */
1415 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1417 /* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */
1422 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1424 /* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */
1429 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1431 /* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */
1436 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1438 /* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */
1443 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1445 /* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */
1450 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1452 /* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */
1457 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1459 /* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */
1464 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1466 /* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */
1471 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1473 /* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */
1478 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1862 /* Description: Enable interrupt */
1864 /* Bit 31 : Write '1' to enable interrupt for PORT event */
1869 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1871 /* Bit 7 : Write '1' to enable interrupt for IN[7] event */
1876 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1878 /* Bit 6 : Write '1' to enable interrupt for IN[6] event */
1883 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1885 /* Bit 5 : Write '1' to enable interrupt for IN[5] event */
1890 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1892 /* Bit 4 : Write '1' to enable interrupt for IN[4] event */
1897 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1899 /* Bit 3 : Write '1' to enable interrupt for IN[3] event */
1904 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1906 /* Bit 2 : Write '1' to enable interrupt for IN[2] event */
1911 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1913 /* Bit 1 : Write '1' to enable interrupt for IN[1] event */
1918 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1920 /* Bit 0 : Write '1' to enable interrupt for IN[0] event */
1925 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
3879 /* Description: Enable or disable interrupt */
3881 /* Bit 2 : Enable or disable interrupt for END event */
3885 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
3887 /* Bit 1 : Enable or disable interrupt for STOPPED event */
3891 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
3893 /* Bit 0 : Enable or disable interrupt for STARTED event */
3897 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
3900 /* Description: Enable interrupt */
3902 /* Bit 2 : Write '1' to enable interrupt for END event */
3907 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
3909 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
3914 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
3916 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
3921 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
3948 /* Description: PDM module enable register */
3950 /* Bit 0 : Enable or disable PDM module */
3951 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
3952 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
3954 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
4046 /* Description: Enable constant latency mode */
4053 /* Description: Enable low power mode (variable latency) */
4081 /* Description: Enable interrupt */
4083 /* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */
4088 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
4090 /* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */
4095 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
4097 /* Bit 2 : Write '1' to enable interrupt for POFWARN event */
4102 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
4170 /* Bit 0 : Enable System OFF mode */
4173 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
4194 /* Bit 0 : Enable or disable power failure comparator */
4198 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
4215 /* Description: DC/DC enable register */
4217 /* Bit 0 : Enable or disable DC/DC converter */
4221 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
4301 /* Description: Description cluster[n]: Enable channel group n */
4315 /* Description: Channel enable register */
4317 /* Bit 31 : Enable or disable channel 31 */
4321 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
4323 /* Bit 30 : Enable or disable channel 30 */
4327 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
4329 /* Bit 29 : Enable or disable channel 29 */
4333 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
4335 /* Bit 28 : Enable or disable channel 28 */
4339 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
4341 /* Bit 27 : Enable or disable channel 27 */
4345 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
4347 /* Bit 26 : Enable or disable channel 26 */
4351 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
4353 /* Bit 25 : Enable or disable channel 25 */
4357 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
4359 /* Bit 24 : Enable or disable channel 24 */
4363 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
4365 /* Bit 23 : Enable or disable channel 23 */
4369 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
4371 /* Bit 22 : Enable or disable channel 22 */
4375 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
4377 /* Bit 21 : Enable or disable channel 21 */
4381 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
4383 /* Bit 20 : Enable or disable channel 20 */
4387 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
4389 /* Bit 19 : Enable or disable channel 19 */
4393 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
4395 /* Bit 18 : Enable or disable channel 18 */
4399 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
4401 /* Bit 17 : Enable or disable channel 17 */
4405 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
4407 /* Bit 16 : Enable or disable channel 16 */
4411 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
4413 /* Bit 15 : Enable or disable channel 15 */
4417 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
4419 /* Bit 14 : Enable or disable channel 14 */
4423 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
4425 /* Bit 13 : Enable or disable channel 13 */
4429 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
4431 /* Bit 12 : Enable or disable channel 12 */
4435 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
4437 /* Bit 11 : Enable or disable channel 11 */
4441 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
4443 /* Bit 10 : Enable or disable channel 10 */
4447 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
4449 /* Bit 9 : Enable or disable channel 9 */
4453 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
4455 /* Bit 8 : Enable or disable channel 8 */
4459 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
4461 /* Bit 7 : Enable or disable channel 7 */
4465 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
4467 /* Bit 6 : Enable or disable channel 6 */
4471 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
4473 /* Bit 5 : Enable or disable channel 5 */
4477 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
4479 /* Bit 4 : Enable or disable channel 4 */
4483 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
4485 /* Bit 3 : Enable or disable channel 3 */
4489 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
4491 /* Bit 2 : Enable or disable channel 2 */
4495 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
4497 /* Bit 1 : Enable or disable channel 1 */
4501 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
4503 /* Bit 0 : Enable or disable channel 0 */
4507 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
4510 /* Description: Channel enable set register */
4512 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
4517 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
4519 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
4524 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
4526 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
4531 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
4533 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
4538 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
4540 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
4545 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
4547 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
4552 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
4554 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
4559 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
4561 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
4566 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
4568 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
4573 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
4575 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
4580 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
4582 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
4587 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
4589 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
4594 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
4596 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
4601 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
4603 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
4608 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
4610 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
4615 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
4617 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
4622 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
4624 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
4629 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
4631 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
4636 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
4638 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
4643 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
4645 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
4650 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
4652 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
4657 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
4659 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
4664 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
4666 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
4671 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
4673 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
4678 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
4680 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
4685 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
4687 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
4692 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
4694 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
4699 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
4701 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
4706 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
4708 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
4713 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
4715 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
4720 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
4722 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
4727 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
4729 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
4734 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
4737 /* Description: Channel enable clear register */
4739 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
4746 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
4753 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
4760 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
4767 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
4774 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
4781 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
4788 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
4795 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
4802 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
4809 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
4816 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
4823 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
4830 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
4837 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
4844 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
4851 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
4858 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
4865 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
4872 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
4879 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
4886 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
4893 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
4900 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
4907 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
4914 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
4921 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
4928 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
4935 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
4942 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
4949 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
4956 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
5246 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
5252 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
5258 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
5264 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
5270 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
5273 /* Description: Enable or disable interrupt */
5275 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
5279 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
5281 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
5285 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
5287 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
5291 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
5293 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
5297 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
5299 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
5303 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
5305 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
5309 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
5311 /* Bit 1 : Enable or disable interrupt for STOPPED event */
5315 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
5318 /* Description: Enable interrupt */
5320 /* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */
5325 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
5327 /* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */
5332 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
5334 /* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */
5339 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
5341 /* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */
5346 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
5348 /* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */
5353 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
5355 /* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */
5360 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
5362 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
5367 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5422 /* Description: PWM module enable register */
5424 /* Bit 0 : Enable or disable PWM module */
5425 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5426 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5428 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5610 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
5616 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5622 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
5628 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5634 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
5640 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5646 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
5649 /* Description: Enable interrupt */
5651 /* Bit 4 : Write '1' to enable interrupt for STOPPED event */
5656 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5658 /* Bit 3 : Write '1' to enable interrupt for DBLRDY event */
5663 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
5665 /* Bit 2 : Write '1' to enable interrupt for ACCOF event */
5670 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
5672 /* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */
5677 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
5679 /* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */
5684 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
5725 /* Description: Enable the quadrature decoder */
5727 /* Bit 0 : Enable or disable the quadrature decoder */
5728 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5729 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5731 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5837 /* Description: Enable input debounce filters */
5839 /* Bit 0 : Enable input debounce filters */
5871 /* Description: Enable RADIO in TX mode */
5878 /* Description: Enable RADIO in RX mode */
6017 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
6023 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
6029 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
6035 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
6041 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
6047 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
6053 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
6059 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
6062 /* Description: Enable interrupt */
6064 /* Bit 13 : Write '1' to enable interrupt for CRCERROR event */
6069 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
6071 /* Bit 12 : Write '1' to enable interrupt for CRCOK event */
6076 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
6078 /* Bit 10 : Write '1' to enable interrupt for BCMATCH event */
6083 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
6085 /* Bit 7 : Write '1' to enable interrupt for RSSIEND event */
6090 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
6092 /* Bit 6 : Write '1' to enable interrupt for DEVMISS event */
6097 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
6099 /* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */
6104 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
6106 /* Bit 4 : Write '1' to enable interrupt for DISABLED event */
6111 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
6113 /* Bit 3 : Write '1' to enable interrupt for END event */
6118 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
6120 /* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */
6125 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
6127 /* Bit 1 : Write '1' to enable interrupt for ADDRESS event */
6132 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
6134 /* Bit 0 : Write '1' to enable interrupt for READY event */
6139 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
6329 /* Bit 25 : Enable or disable packet whitening */
6333 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
6415 /* Bit 7 : Enable or disable reception on logical address 7. */
6419 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
6421 /* Bit 6 : Enable or disable reception on logical address 6. */
6425 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
6427 /* Bit 5 : Enable or disable reception on logical address 5. */
6431 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
6433 /* Bit 4 : Enable or disable reception on logical address 4. */
6437 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
6439 /* Bit 3 : Enable or disable reception on logical address 3. */
6443 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
6445 /* Bit 2 : Enable or disable reception on logical address 2. */
6449 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
6451 /* Bit 1 : Enable or disable reception on logical address 1. */
6455 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
6457 /* Bit 0 : Enable or disable reception on logical address 0. */
6461 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
6587 /* Bit 7 : Enable or disable device address matching using device address 7 */
6593 /* Bit 6 : Enable or disable device address matching using device address 6 */
6599 /* Bit 5 : Enable or disable device address matching using device address 5 */
6605 /* Bit 4 : Enable or disable device address matching using device address 4 */
6611 /* Bit 3 : Enable or disable device address matching using device address 3 */
6617 /* Bit 2 : Enable or disable device address matching using device address 2 */
6623 /* Bit 1 : Enable or disable device address matching using device address 1 */
6629 /* Bit 0 : Enable or disable device address matching using device address 0 */
6692 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
6695 /* Description: Enable interrupt */
6697 /* Bit 0 : Write '1' to enable interrupt for VALRDY event */
6702 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
6784 /* Description: Enable interrupt */
6786 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
6791 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
6793 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
6798 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
6800 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
6805 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
6807 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
6812 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
6814 /* Bit 1 : Write '1' to enable interrupt for OVRFLW event */
6819 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
6821 /* Bit 0 : Write '1' to enable interrupt for TICK event */
6826 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
6874 /* Description: Enable or disable event routing */
6876 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
6880 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
6882 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
6886 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
6888 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
6892 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
6894 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
6898 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
6900 /* Bit 1 : Enable or disable event routing for OVRFLW event */
6904 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
6906 /* Bit 0 : Enable or disable event routing for TICK event */
6910 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
6913 /* Description: Enable event routing */
6915 /* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */
6920 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
6922 /* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */
6927 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
6929 /* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */
6934 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
6936 /* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */
6941 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
6943 /* Bit 1 : Write '1' to enable event routing for OVRFLW event */
6948 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
6950 /* Bit 0 : Write '1' to enable event routing for TICK event */
6955 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
7112 /* Description: Enable or disable interrupt */
7114 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
7118 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
7120 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
7124 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
7126 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
7130 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
7132 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
7136 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
7138 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
7142 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
7144 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
7148 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
7150 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
7154 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
7156 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
7160 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
7162 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
7166 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
7168 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
7172 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
7174 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
7178 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
7180 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
7184 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
7186 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
7190 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
7192 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
7196 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
7198 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
7202 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
7204 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
7208 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
7210 /* Bit 5 : Enable or disable interrupt for STOPPED event */
7214 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
7216 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
7220 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
7222 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
7226 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
7228 /* Bit 2 : Enable or disable interrupt for DONE event */
7232 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
7234 /* Bit 1 : Enable or disable interrupt for END event */
7238 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
7240 /* Bit 0 : Enable or disable interrupt for STARTED event */
7244 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
7247 /* Description: Enable interrupt */
7249 /* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */
7254 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
7256 /* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */
7261 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
7263 /* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */
7268 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
7270 /* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */
7275 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
7277 /* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */
7282 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
7284 /* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */
7289 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
7291 /* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */
7296 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
7298 /* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */
7303 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
7305 /* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */
7310 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
7312 /* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */
7317 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
7319 /* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */
7324 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
7326 /* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */
7331 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
7333 /* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */
7338 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
7340 /* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */
7345 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
7347 /* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */
7352 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
7354 /* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */
7359 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
7361 /* Bit 5 : Write '1' to enable interrupt for STOPPED event */
7366 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7368 /* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */
7373 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
7375 /* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */
7380 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
7382 /* Bit 2 : Write '1' to enable interrupt for DONE event */
7387 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
7389 /* Bit 1 : Write '1' to enable interrupt for END event */
7394 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
7396 /* Bit 0 : Write '1' to enable interrupt for STARTED event */
7401 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
7570 /* Description: Enable or disable ADC */
7572 /* Bit 0 : Enable or disable ADC */
7573 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7574 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7576 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
7615 /* Bit 24 : Enable burst mode */
7621 /* Bit 20 : Enable differential mode */
7817 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
7820 /* Description: Enable interrupt */
7822 /* Bit 19 : Write '1' to enable interrupt for STARTED event */
7827 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
7829 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
7834 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
7836 /* Bit 6 : Write '1' to enable interrupt for END event */
7841 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
7843 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
7848 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7850 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
7855 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7896 /* Description: Enable SPIM */
7898 /* Bits 3..0 : Enable or disable SPIM */
7899 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7900 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7902 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
8091 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
8094 /* Description: Enable interrupt */
8096 /* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */
8101 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
8103 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
8108 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
8110 /* Bit 1 : Write '1' to enable interrupt for END event */
8115 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
8170 /* Description: Enable SPI slave */
8172 /* Bits 3..0 : Enable or disable SPI slave */
8173 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8174 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8176 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
8333 /* Description: Enable interrupt */
8335 /* Bit 0 : Write '1' to enable interrupt for DATARDY event */
8340 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
8538 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
8544 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
8550 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
8556 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
8562 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
8568 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
8574 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8580 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8586 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8592 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8598 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8604 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8607 /* Description: Enable interrupt */
8609 /* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */
8614 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
8616 /* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */
8621 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
8623 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */
8628 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
8630 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */
8635 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
8637 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */
8642 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
8644 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */
8649 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
8826 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
8832 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8838 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
8844 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
8850 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8856 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
8859 /* Description: Enable or disable interrupt */
8861 /* Bit 24 : Enable or disable interrupt for LASTTX event */
8865 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
8867 /* Bit 23 : Enable or disable interrupt for LASTRX event */
8871 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
8873 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
8877 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
8879 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
8883 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
8885 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
8889 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
8891 /* Bit 9 : Enable or disable interrupt for ERROR event */
8895 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
8897 /* Bit 1 : Enable or disable interrupt for STOPPED event */
8901 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8904 /* Description: Enable interrupt */
8906 /* Bit 24 : Write '1' to enable interrupt for LASTTX event */
8911 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
8913 /* Bit 23 : Write '1' to enable interrupt for LASTRX event */
8918 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
8920 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
8925 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
8927 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
8932 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
8934 /* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */
8939 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
8941 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
8946 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
8948 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
8953 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9029 /* Description: Enable TWIM */
9031 /* Bits 3..0 : Enable or disable TWIM */
9032 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9033 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9035 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
9228 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9234 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9237 /* Description: Enable or disable interrupt */
9239 /* Bit 26 : Enable or disable interrupt for READ event */
9243 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
9245 /* Bit 25 : Enable or disable interrupt for WRITE event */
9249 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
9251 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
9255 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9257 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
9261 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9263 /* Bit 9 : Enable or disable interrupt for ERROR event */
9267 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9269 /* Bit 1 : Enable or disable interrupt for STOPPED event */
9273 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9276 /* Description: Enable interrupt */
9278 /* Bit 26 : Write '1' to enable interrupt for READ event */
9283 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
9285 /* Bit 25 : Write '1' to enable interrupt for WRITE event */
9290 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
9292 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
9297 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9299 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
9304 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9306 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
9311 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
9313 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */
9318 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9394 /* Description: Enable TWIS */
9396 /* Bits 3..0 : Enable or disable TWIS */
9397 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9398 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9400 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
9480 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9486 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
9622 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
9628 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
9631 /* Description: Enable or disable interrupt */
9633 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
9637 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
9639 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
9643 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9645 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
9649 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9651 /* Bit 17 : Enable or disable interrupt for RXTO event */
9655 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
9657 /* Bit 9 : Enable or disable interrupt for ERROR event */
9661 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9663 /* Bit 8 : Enable or disable interrupt for ENDTX event */
9667 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
9669 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
9673 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
9675 /* Bit 4 : Enable or disable interrupt for ENDRX event */
9679 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
9681 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
9685 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
9687 /* Bit 1 : Enable or disable interrupt for NCTS event */
9691 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
9693 /* Bit 0 : Enable or disable interrupt for CTS event */
9697 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
9700 /* Description: Enable interrupt */
9702 /* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */
9707 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
9709 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */
9714 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9716 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */
9721 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9723 /* Bit 17 : Write '1' to enable interrupt for RXTO event */
9728 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
9730 /* Bit 9 : Write '1' to enable interrupt for ERROR event */
9735 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
9737 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */
9742 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
9744 /* Bit 7 : Write '1' to enable interrupt for TXDRDY event */
9749 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
9751 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */
9756 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
9758 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */
9763 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
9765 /* Bit 1 : Write '1' to enable interrupt for NCTS event */
9770 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
9772 /* Bit 0 : Write '1' to enable interrupt for CTS event */
9777 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
9887 /* Description: Enable UART */
9889 /* Bits 3..0 : Enable or disable UARTE */
9890 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9891 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9893 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
10076 /* Bits 7..0 : Enable or disable access port protection. */
10079 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
10101 /* Description: Enable interrupt */
10103 /* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */
10108 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
10188 /* Description: Enable register for reload request registers */
10190 /* Bit 7 : Enable or disable RR[7] register */
10194 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
10196 /* Bit 6 : Enable or disable RR[6] register */
10200 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
10202 /* Bit 5 : Enable or disable RR[5] register */
10206 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
10208 /* Bit 4 : Enable or disable RR[4] register */
10212 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
10214 /* Bit 3 : Enable or disable RR[3] register */
10218 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
10220 /* Bit 2 : Enable or disable RR[2] register */
10224 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
10226 /* Bit 1 : Enable or disable RR[1] register */
10230 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
10232 /* Bit 0 : Enable or disable RR[0] register */
10236 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */