Lines Matching full:disable

101 /* Description: Disable interrupt */
103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */
108 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
110 /* Bit 1 : Write '1' to disable interrupt for RESOLVED event */
115 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
117 /* Bit 0 : Write '1' to disable interrupt for END event */
122 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
134 /* Bits 1..0 : Enable or disable AAR */
137 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
467 /* Description: Disable protection mechanism in debug mode */
469 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will…
534 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
562 /* Description: Disable interrupt */
564 /* Bit 2 : Write '1' to disable interrupt for ERROR event */
569 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
571 /* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */
576 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
578 /* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */
583 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
597 /* Bits 1..0 : Enable or disable CCM */
600 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
786 /* Description: Disable interrupt */
788 /* Bit 4 : Write '1' to disable interrupt for CTTO event */
793 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
795 /* Bit 3 : Write '1' to disable interrupt for DONE event */
800 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
802 /* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */
807 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
809 /* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */
814 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
878 /* Bit 17 : Enable or disable external source for LFCLK */
881 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
884 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
887 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external sour…
963 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
969 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
975 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
981 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
987 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
991 /* Description: Enable or disable interrupt */
993 /* Bit 3 : Enable or disable interrupt for CROSS event */
996 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
999 /* Bit 2 : Enable or disable interrupt for UP event */
1002 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1005 /* Bit 1 : Enable or disable interrupt for DOWN event */
1008 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1011 /* Bit 0 : Enable or disable interrupt for READY event */
1014 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1049 /* Description: Disable interrupt */
1051 /* Bit 3 : Write '1' to disable interrupt for CROSS event */
1056 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1058 /* Bit 2 : Write '1' to disable interrupt for UP event */
1063 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1065 /* Bit 1 : Write '1' to disable interrupt for DOWN event */
1070 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1072 /* Bit 0 : Write '1' to disable interrupt for READY event */
1077 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1091 /* Bits 1..0 : Enable or disable COMP */
1094 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1225 /* Description: Disable interrupt */
1227 /* Bit 1 : Write '1' to disable interrupt for ERRORECB event */
1232 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1234 /* Bit 0 : Write '1' to disable interrupt for ENDECB event */
1239 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1267 /* Description: Enable or disable interrupt */
1269 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1272 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1275 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1278 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1281 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1284 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1287 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1290 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1293 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1296 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1299 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1302 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1305 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1308 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1311 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1314 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1317 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1320 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1323 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1326 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1329 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1332 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1335 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1338 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1341 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1344 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1347 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1350 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1353 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1356 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1359 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1362 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1481 /* Description: Disable interrupt */
1483 /* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */
1488 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1490 /* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */
1495 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1497 /* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */
1502 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1504 /* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */
1509 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1511 /* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */
1516 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1518 /* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */
1523 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1525 /* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */
1530 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1532 /* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */
1537 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1539 /* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */
1544 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1546 /* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */
1551 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1553 /* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */
1558 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1560 /* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */
1565 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1567 /* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */
1572 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1574 /* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */
1579 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1581 /* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */
1586 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1588 /* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */
1593 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1928 /* Description: Disable interrupt */
1930 /* Bit 31 : Write '1' to disable interrupt for PORT event */
1935 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1937 /* Bit 7 : Write '1' to disable interrupt for IN[7] event */
1942 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1944 /* Bit 6 : Write '1' to disable interrupt for IN[6] event */
1949 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1951 /* Bit 5 : Write '1' to disable interrupt for IN[5] event */
1956 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1958 /* Bit 4 : Write '1' to disable interrupt for IN[4] event */
1963 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
1965 /* Bit 3 : Write '1' to disable interrupt for IN[3] event */
1970 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
1972 /* Bit 2 : Write '1' to disable interrupt for IN[2] event */
1977 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
1979 /* Bit 1 : Write '1' to disable interrupt for IN[1] event */
1984 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
1986 /* Bit 0 : Write '1' to disable interrupt for IN[0] event */
1991 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
3879 /* Description: Enable or disable interrupt */
3881 /* Bit 2 : Enable or disable interrupt for END event */
3884 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
3887 /* Bit 1 : Enable or disable interrupt for STOPPED event */
3890 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
3893 /* Bit 0 : Enable or disable interrupt for STARTED event */
3896 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
3924 /* Description: Disable interrupt */
3926 /* Bit 2 : Write '1' to disable interrupt for END event */
3931 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
3933 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
3938 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
3940 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
3945 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
3950 /* Bit 0 : Enable or disable PDM module */
3953 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
4105 /* Description: Disable interrupt */
4107 /* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */
4112 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
4114 /* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */
4119 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
4121 /* Bit 2 : Write '1' to disable interrupt for POFWARN event */
4126 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
4194 /* Bit 0 : Enable or disable power failure comparator */
4197 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
4217 /* Bit 0 : Enable or disable DC/DC converter */
4220 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
4308 /* Description: Description cluster[n]: Disable channel group n */
4317 /* Bit 31 : Enable or disable channel 31 */
4320 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
4323 /* Bit 30 : Enable or disable channel 30 */
4326 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
4329 /* Bit 29 : Enable or disable channel 29 */
4332 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
4335 /* Bit 28 : Enable or disable channel 28 */
4338 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
4341 /* Bit 27 : Enable or disable channel 27 */
4344 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
4347 /* Bit 26 : Enable or disable channel 26 */
4350 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
4353 /* Bit 25 : Enable or disable channel 25 */
4356 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
4359 /* Bit 24 : Enable or disable channel 24 */
4362 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
4365 /* Bit 23 : Enable or disable channel 23 */
4368 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
4371 /* Bit 22 : Enable or disable channel 22 */
4374 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
4377 /* Bit 21 : Enable or disable channel 21 */
4380 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
4383 /* Bit 20 : Enable or disable channel 20 */
4386 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
4389 /* Bit 19 : Enable or disable channel 19 */
4392 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
4395 /* Bit 18 : Enable or disable channel 18 */
4398 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
4401 /* Bit 17 : Enable or disable channel 17 */
4404 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
4407 /* Bit 16 : Enable or disable channel 16 */
4410 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
4413 /* Bit 15 : Enable or disable channel 15 */
4416 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
4419 /* Bit 14 : Enable or disable channel 14 */
4422 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
4425 /* Bit 13 : Enable or disable channel 13 */
4428 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
4431 /* Bit 12 : Enable or disable channel 12 */
4434 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
4437 /* Bit 11 : Enable or disable channel 11 */
4440 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
4443 /* Bit 10 : Enable or disable channel 10 */
4446 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
4449 /* Bit 9 : Enable or disable channel 9 */
4452 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
4455 /* Bit 8 : Enable or disable channel 8 */
4458 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
4461 /* Bit 7 : Enable or disable channel 7 */
4464 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
4467 /* Bit 6 : Enable or disable channel 6 */
4470 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
4473 /* Bit 5 : Enable or disable channel 5 */
4476 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
4479 /* Bit 4 : Enable or disable channel 4 */
4482 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
4485 /* Bit 3 : Enable or disable channel 3 */
4488 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
4491 /* Bit 2 : Enable or disable channel 2 */
4494 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
4497 /* Bit 1 : Enable or disable channel 1 */
4500 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
4503 /* Bit 0 : Enable or disable channel 0 */
4506 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
4744 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
4751 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
4758 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
4765 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
4772 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
4779 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
4786 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
4793 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
4800 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
4807 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
4814 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
4821 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
4828 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
4835 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
4842 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
4849 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
4856 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
4863 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
4870 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
4877 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
4884 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
4891 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
4898 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
4905 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
4912 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
4919 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
4926 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
4933 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
4940 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
4947 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
4954 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
4961 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
5245 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
5251 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
5257 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
5263 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
5269 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
5273 /* Description: Enable or disable interrupt */
5275 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
5278 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
5281 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
5284 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
5287 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
5290 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
5293 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
5296 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
5299 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
5302 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
5305 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
5308 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
5311 /* Bit 1 : Enable or disable interrupt for STOPPED event */
5314 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
5370 /* Description: Disable interrupt */
5372 /* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */
5377 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
5379 /* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */
5384 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
5386 /* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */
5391 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
5393 /* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */
5398 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
5400 /* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */
5405 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
5407 /* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */
5412 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
5414 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
5419 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5424 /* Bit 0 : Enable or disable PWM module */
5609 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
5615 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5621 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
5627 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5633 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
5639 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5645 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
5687 /* Description: Disable interrupt */
5689 /* Bit 4 : Write '1' to disable interrupt for STOPPED event */
5694 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5696 /* Bit 3 : Write '1' to disable interrupt for DBLRDY event */
5701 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
5703 /* Bit 2 : Write '1' to disable interrupt for ACCOF event */
5708 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
5710 /* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */
5715 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
5717 /* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */
5722 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
5727 /* Bit 0 : Enable or disable the quadrature decoder */
5730 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
5899 /* Description: Disable RADIO */
6016 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
6022 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
6028 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
6034 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
6040 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
6046 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
6049 /* Bit 1 : Shortcut between END event and DISABLE task */
6052 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
6058 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
6142 /* Description: Disable interrupt */
6144 /* Bit 13 : Write '1' to disable interrupt for CRCERROR event */
6149 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
6151 /* Bit 12 : Write '1' to disable interrupt for CRCOK event */
6156 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
6158 /* Bit 10 : Write '1' to disable interrupt for BCMATCH event */
6163 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
6165 /* Bit 7 : Write '1' to disable interrupt for RSSIEND event */
6170 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
6172 /* Bit 6 : Write '1' to disable interrupt for DEVMISS event */
6177 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
6179 /* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */
6184 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
6186 /* Bit 4 : Write '1' to disable interrupt for DISABLED event */
6191 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
6193 /* Bit 3 : Write '1' to disable interrupt for END event */
6198 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
6200 /* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */
6205 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
6207 /* Bit 1 : Write '1' to disable interrupt for ADDRESS event */
6212 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
6214 /* Bit 0 : Write '1' to disable interrupt for READY event */
6219 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
6329 /* Bit 25 : Enable or disable packet whitening */
6332 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
6415 /* Bit 7 : Enable or disable reception on logical address 7. */
6418 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
6421 /* Bit 6 : Enable or disable reception on logical address 6. */
6424 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
6427 /* Bit 5 : Enable or disable reception on logical address 5. */
6430 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
6433 /* Bit 4 : Enable or disable reception on logical address 4. */
6436 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
6439 /* Bit 3 : Enable or disable reception on logical address 3. */
6442 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
6445 /* Bit 2 : Enable or disable reception on logical address 2. */
6448 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
6451 /* Bit 1 : Enable or disable reception on logical address 1. */
6454 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
6457 /* Bit 0 : Enable or disable reception on logical address 0. */
6460 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
6587 /* Bit 7 : Enable or disable device address matching using device address 7 */
6593 /* Bit 6 : Enable or disable device address matching using device address 6 */
6599 /* Bit 5 : Enable or disable device address matching using device address 5 */
6605 /* Bit 4 : Enable or disable device address matching using device address 4 */
6611 /* Bit 3 : Enable or disable device address matching using device address 3 */
6617 /* Bit 2 : Enable or disable device address matching using device address 2 */
6623 /* Bit 1 : Enable or disable device address matching using device address 1 */
6629 /* Bit 0 : Enable or disable device address matching using device address 0 */
6691 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
6705 /* Description: Disable interrupt */
6707 /* Bit 0 : Write '1' to disable interrupt for VALRDY event */
6712 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
6829 /* Description: Disable interrupt */
6831 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
6836 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
6838 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
6843 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
6845 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
6850 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
6852 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
6857 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
6859 /* Bit 1 : Write '1' to disable interrupt for OVRFLW event */
6864 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
6866 /* Bit 0 : Write '1' to disable interrupt for TICK event */
6871 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
6874 /* Description: Enable or disable event routing */
6876 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
6879 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
6882 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
6885 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
6888 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
6891 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
6894 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
6897 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
6900 /* Bit 1 : Enable or disable event routing for OVRFLW event */
6903 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
6906 /* Bit 0 : Enable or disable event routing for TICK event */
6909 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
6958 /* Description: Disable event routing */
6960 /* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */
6965 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
6967 /* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */
6972 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
6974 /* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */
6979 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
6981 /* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */
6986 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
6988 /* Bit 1 : Write '1' to disable event routing for OVRFLW event */
6993 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
6995 /* Bit 0 : Write '1' to disable event routing for TICK event */
7000 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
7112 /* Description: Enable or disable interrupt */
7114 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
7117 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
7120 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
7123 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
7126 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
7129 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
7132 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
7135 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
7138 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
7141 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
7144 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
7147 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
7150 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
7153 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
7156 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
7159 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
7162 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
7165 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
7168 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
7171 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
7174 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
7177 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
7180 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
7183 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
7186 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
7189 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
7192 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
7195 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
7198 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
7201 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
7204 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
7207 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
7210 /* Bit 5 : Enable or disable interrupt for STOPPED event */
7213 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
7216 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
7219 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
7222 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
7225 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
7228 /* Bit 2 : Enable or disable interrupt for DONE event */
7231 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
7234 /* Bit 1 : Enable or disable interrupt for END event */
7237 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
7240 /* Bit 0 : Enable or disable interrupt for STARTED event */
7243 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
7404 /* Description: Disable interrupt */
7406 /* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */
7411 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
7413 /* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */
7418 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
7420 /* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */
7425 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
7427 /* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */
7432 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
7434 /* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */
7439 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
7441 /* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */
7446 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
7448 /* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */
7453 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
7455 /* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */
7460 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
7462 /* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */
7467 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
7469 /* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */
7474 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
7476 /* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */
7481 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
7483 /* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */
7488 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
7490 /* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */
7495 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
7497 /* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */
7502 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
7504 /* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */
7509 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
7511 /* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */
7516 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
7518 /* Bit 5 : Write '1' to disable interrupt for STOPPED event */
7523 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7525 /* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */
7530 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
7532 /* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */
7537 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
7539 /* Bit 2 : Write '1' to disable interrupt for DONE event */
7544 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
7546 /* Bit 1 : Write '1' to disable interrupt for END event */
7551 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
7553 /* Bit 0 : Write '1' to disable interrupt for STARTED event */
7558 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7570 /* Description: Enable or disable ADC */
7572 /* Bit 0 : Enable or disable ADC */
7575 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
7816 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
7858 /* Description: Disable interrupt */
7860 /* Bit 19 : Write '1' to disable interrupt for STARTED event */
7865 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7867 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
7872 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
7874 /* Bit 6 : Write '1' to disable interrupt for END event */
7879 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
7881 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
7886 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7888 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
7893 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7898 /* Bits 3..0 : Enable or disable SPIM */
7901 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
7984 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
8014 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
8090 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
8118 /* Description: Disable interrupt */
8120 /* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */
8125 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
8127 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
8132 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
8134 /* Bit 1 : Write '1' to disable interrupt for END event */
8139 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
8172 /* Bits 3..0 : Enable or disable SPI slave */
8175 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
8343 /* Description: Disable interrupt */
8345 /* Bit 0 : Write '1' to disable interrupt for DATARDY event */
8350 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
8537 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
8543 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
8549 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
8555 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
8561 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
8567 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
8573 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8579 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8585 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8591 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8597 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8603 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8652 /* Description: Disable interrupt */
8654 /* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */
8659 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
8661 /* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */
8666 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
8668 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */
8673 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8675 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */
8680 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8682 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */
8687 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8689 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */
8694 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8825 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
8831 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8837 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
8843 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
8849 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8855 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
8859 /* Description: Enable or disable interrupt */
8861 /* Bit 24 : Enable or disable interrupt for LASTTX event */
8864 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
8867 /* Bit 23 : Enable or disable interrupt for LASTRX event */
8870 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
8873 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
8876 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
8879 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
8882 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
8885 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
8888 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
8891 /* Bit 9 : Enable or disable interrupt for ERROR event */
8894 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
8897 /* Bit 1 : Enable or disable interrupt for STOPPED event */
8900 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8956 /* Description: Disable interrupt */
8958 /* Bit 24 : Write '1' to disable interrupt for LASTTX event */
8963 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
8965 /* Bit 23 : Write '1' to disable interrupt for LASTRX event */
8970 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
8972 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
8977 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
8979 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
8984 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
8986 /* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */
8991 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
8993 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
8998 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9000 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
9005 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9031 /* Bits 3..0 : Enable or disable TWIM */
9034 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
9100 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9130 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9227 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9233 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9237 /* Description: Enable or disable interrupt */
9239 /* Bit 26 : Enable or disable interrupt for READ event */
9242 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
9245 /* Bit 25 : Enable or disable interrupt for WRITE event */
9248 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
9251 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
9254 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9257 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
9260 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9263 /* Bit 9 : Enable or disable interrupt for ERROR event */
9266 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9269 /* Bit 1 : Enable or disable interrupt for STOPPED event */
9272 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9321 /* Description: Disable interrupt */
9323 /* Bit 26 : Write '1' to disable interrupt for READ event */
9328 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
9330 /* Bit 25 : Write '1' to disable interrupt for WRITE event */
9335 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
9337 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
9342 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9344 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
9349 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9351 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
9356 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9358 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */
9363 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9396 /* Bits 3..0 : Enable or disable TWIS */
9399 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
9480 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9486 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
9621 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
9627 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
9631 /* Description: Enable or disable interrupt */
9633 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
9636 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
9639 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
9642 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9645 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
9648 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9651 /* Bit 17 : Enable or disable interrupt for RXTO event */
9654 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
9657 /* Bit 9 : Enable or disable interrupt for ERROR event */
9660 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9663 /* Bit 8 : Enable or disable interrupt for ENDTX event */
9666 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
9669 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
9672 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
9675 /* Bit 4 : Enable or disable interrupt for ENDRX event */
9678 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
9681 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
9684 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
9687 /* Bit 1 : Enable or disable interrupt for NCTS event */
9690 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
9693 /* Bit 0 : Enable or disable interrupt for CTS event */
9696 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
9780 /* Description: Disable interrupt */
9782 /* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */
9787 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
9789 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */
9794 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9796 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */
9801 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9803 /* Bit 17 : Write '1' to disable interrupt for RXTO event */
9808 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
9810 /* Bit 9 : Write '1' to disable interrupt for ERROR event */
9815 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9817 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */
9822 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
9824 /* Bit 7 : Write '1' to disable interrupt for TXDRDY event */
9829 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
9831 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */
9836 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
9838 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */
9843 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
9845 /* Bit 1 : Write '1' to disable interrupt for NCTS event */
9850 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
9852 /* Bit 0 : Write '1' to disable interrupt for CTS event */
9857 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
9889 /* Bits 3..0 : Enable or disable UARTE */
9892 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
10076 /* Bits 7..0 : Enable or disable access port protection. */
10080 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
10111 /* Description: Disable interrupt */
10113 /* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */
10118 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
10190 /* Bit 7 : Enable or disable RR[7] register */
10193 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
10196 /* Bit 6 : Enable or disable RR[6] register */
10199 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
10202 /* Bit 5 : Enable or disable RR[5] register */
10205 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
10208 /* Bit 4 : Enable or disable RR[4] register */
10211 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
10214 /* Bit 3 : Enable or disable RR[3] register */
10217 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
10220 /* Bit 2 : Enable or disable RR[2] register */
10223 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
10226 /* Bit 1 : Enable or disable RR[1] register */
10229 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
10232 /* Bit 0 : Enable or disable RR[0] register */
10235 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */