Lines Matching full:description

39 /* Description: Accelerated Address Resolver */
42 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
49 /* Description: Stop resolving addresses */
56 /* Description: Address resolution procedure complete */
63 /* Description: Address resolved */
70 /* Description: Address not resolved */
77 /* Description: Enable interrupt */
101 /* Description: Disable interrupt */
125 /* Description: Resolution status */
132 /* Description: Enable AAR */
141 /* Description: Number of IRKs */
148 /* Description: Pointer to IRK data structure */
155 /* Description: Pointer to the resolvable address */
162 /* Description: Pointer to data area used for temporary storage */
170 /* Description: Block Protect */
173 /* Description: Block protect configuration register 0 */
368 /* Description: Block protect configuration register 1 */
467 /* Description: Disable protection mechanism in debug mode */
477 /* Description: AES CCM Mode Encryption */
480 /* Description: Start generation of key-stream. This operation will stop by itself when completed. …
487 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
494 /* Description: Stop encryption/decryption */
501 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE re…
508 /* Description: Key-stream generation complete */
515 /* Description: Encrypt/decrypt complete */
522 /* Description: Deprecated register - CCM error event */
529 /* Description: Shortcut register */
538 /* Description: Enable interrupt */
562 /* Description: Disable interrupt */
586 /* Description: MIC check result */
595 /* Description: Enable */
604 /* Description: Operation mode */
627 /* Description: Pointer to data structure holding AES key and NONCE vector */
634 /* Description: Input pointer */
641 /* Description: Output pointer */
648 /* Description: Pointer to data area used for temporary storage */
656 /* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
663 /* Description: Data rate override setting. */
675 /* Description: Clock control */
678 /* Description: Start HFCLK crystal oscillator */
685 /* Description: Stop HFCLK crystal oscillator */
692 /* Description: Start LFCLK source */
699 /* Description: Stop LFCLK source */
706 /* Description: Start calibration of LFRC oscillator */
713 /* Description: Start calibration timer */
720 /* Description: Stop calibration timer */
727 /* Description: HFCLK oscillator started */
734 /* Description: LFCLK started */
741 /* Description: Calibration of LFCLK RC oscillator complete event */
748 /* Description: Calibration timer timeout */
755 /* Description: Enable interrupt */
786 /* Description: Disable interrupt */
817 /* Description: Status indicating that HFCLKSTART task has been triggered */
826 /* Description: HFCLK status */
841 /* Description: Status indicating that LFCLKSTART task has been triggered */
850 /* Description: LFCLK status */
866 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
876 /* Description: Clock source for the LFCLK */
898 /* Description: Calibration timer interval */
906 /* Description: Comparator */
909 /* Description: Start comparator */
916 /* Description: Stop comparator */
923 /* Description: Sample comparator value */
930 /* Description: COMP is ready and output is valid */
937 /* Description: Downward crossing */
944 /* Description: Upward crossing */
951 /* Description: Downward or upward crossing */
958 /* Description: Shortcut register */
991 /* Description: Enable or disable interrupt */
1018 /* Description: Enable interrupt */
1049 /* Description: Disable interrupt */
1080 /* Description: Compare result */
1089 /* Description: COMP enable */
1098 /* Description: Pin select */
1113 /* Description: Reference source select for single-ended mode */
1125 /* Description: External reference select */
1140 /* Description: Threshold configuration for hysteresis unit */
1151 /* Description: Mode configuration */
1167 /* Description: Comparator hysteresis enable */
1177 /* Description: AES ECB Mode Encryption */
1180 /* Description: Start ECB block encrypt */
1187 /* Description: Abort a possible executing ECB operation */
1194 /* Description: ECB block encrypt complete */
1201 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1208 /* Description: Enable interrupt */
1225 /* Description: Disable interrupt */
1242 /* Description: ECB block encrypt memory pointers */
1250 /* Description: Event Generator Unit 0 */
1253 /* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] …
1260 /* Description: Description collection[n]: Event number n generated by triggering the corresponding…
1267 /* Description: Enable or disable interrupt */
1366 /* Description: Enable interrupt */
1481 /* Description: Disable interrupt */
1597 /* Description: Factory information configuration registers */
1600 /* Description: Code memory page size */
1607 /* Description: Code memory size */
1614 /* Description: Description collection[n]: Device identifier */
1621 /* Description: Description collection[n]: Encryption root, word n */
1628 /* Description: Description collection[n]: Identity root, word n */
1635 /* Description: Device address type */
1644 /* Description: Description collection[n]: Device address n */
1651 /* Description: Part code */
1660 /* Description: Part variant, hardware version and production configuration */
1676 /* Description: Package option */
1686 /* Description: RAM variant */
1695 /* Description: Flash variant */
1704 /* Description: Slope definition A0 */
1711 /* Description: Slope definition A1 */
1718 /* Description: Slope definition A2 */
1725 /* Description: Slope definition A3 */
1732 /* Description: Slope definition A4 */
1739 /* Description: Slope definition A5 */
1746 /* Description: Y-intercept B0 */
1753 /* Description: Y-intercept B1 */
1760 /* Description: Y-intercept B2 */
1767 /* Description: Y-intercept B3 */
1774 /* Description: Y-intercept B4 */
1781 /* Description: Y-intercept B5 */
1788 /* Description: Segment end T0 */
1795 /* Description: Segment end T1 */
1802 /* Description: Segment end T2 */
1809 /* Description: Segment end T3 */
1816 /* Description: Segment end T4 */
1824 /* Description: GPIO Tasks and Events */
1827 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Act…
1834 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Act…
1841 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Act…
1848 /* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */
1855 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1862 /* Description: Enable interrupt */
1928 /* Description: Disable interrupt */
1994 /* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN…
2023 /* Description: Non-volatile memory controller */
2026 /* Description: Ready flag */
2035 /* Description: Configuration register */
2045 /* Description: Register for erasing a page in code area */
2052 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
2059 /* Description: Register for erasing all non-volatile user memory */
2068 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
2075 /* Description: Register for erasing user information configuration registers */
2084 /* Description: Register for partial erase of a page in code area */
2091 /* Description: Register for partial erase configuration */
2099 /* Description: GPIO Port */
2102 /* Description: Write GPIO port */
2297 /* Description: Set individual bits in GPIO port */
2524 /* Description: Clear individual bits in GPIO port */
2751 /* Description: Read GPIO port */
2946 /* Description: Direction of GPIO pins */
3141 /* Description: DIR set register */
3368 /* Description: DIR clear register */
3595 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_…
3790 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
3799 /* Description: Description collection[n]: Configuration of GPIO pins */
3841 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
3844 /* Description: Starts continuous PDM transfer */
3851 /* Description: Stops PDM transfer */
3858 /* Description: PDM transfer has started */
3865 /* Description: PDM transfer has finished */
3872 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample …
3879 /* Description: Enable or disable interrupt */
3900 /* Description: Enable interrupt */
3924 /* Description: Disable interrupt */
3948 /* Description: PDM module enable register */
3957 /* Description: PDM clock generator control */
3967 /* Description: Defines the routing of the connected PDM microphones' signals */
3982 /* Description: Left output gain adjustment */
3992 /* Description: Right output gain adjustment */
4002 /* Description: Pin number configuration for PDM CLK signal */
4015 /* Description: Pin number configuration for PDM DIN signal */
4028 /* Description: RAM address pointer to write samples to with EasyDMA */
4035 /* Description: Number of samples to allocate memory for in EasyDMA mode */
4043 /* Description: Power control */
4046 /* Description: Enable constant latency mode */
4053 /* Description: Enable low power mode (variable latency) */
4060 /* Description: Power failure warning */
4067 /* Description: CPU entered WFI/WFE sleep */
4074 /* Description: CPU exited WFI/WFE sleep */
4081 /* Description: Enable interrupt */
4105 /* Description: Disable interrupt */
4129 /* Description: Reset reason */
4168 /* Description: System OFF register */
4176 /* Description: Power failure comparator configuration */
4201 /* Description: General purpose retention register */
4208 /* Description: General purpose retention register */
4215 /* Description: DC/DC enable register */
4224 /* Description: Description cluster[n]: RAMn power control register. The RAM size will vary dependi…
4251 /* Description: Description cluster[n]: RAMn power control set register */
4274 /* Description: Description cluster[n]: RAMn power control clear register */
4298 /* Description: Programmable Peripheral Interconnect */
4301 /* Description: Description cluster[n]: Enable channel group n */
4308 /* Description: Description cluster[n]: Disable channel group n */
4315 /* Description: Channel enable register */
4510 /* Description: Channel enable set register */
4737 /* Description: Channel enable clear register */
4964 /* Description: Description cluster[n]: Channel n event end-point */
4971 /* Description: Description cluster[n]: Channel n task end-point */
4978 /* Description: Description collection[n]: Channel group n */
5173 /* Description: Description cluster[n]: Channel n task end-point */
5181 /* Description: Pulse width modulation unit */
5184 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and st…
5191 /* Description: Description collection[n]: Loads the first PWM value on all enabled channels from s…
5198 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=…
5205 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
5212 /* Description: Description collection[n]: First PWM period started on sequence n */
5219 /* Description: Description collection[n]: Emitted at end of every sequence n, when last value from…
5226 /* Description: Emitted at the end of each PWM period */
5233 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
5240 /* Description: Shortcut register */
5273 /* Description: Enable or disable interrupt */
5318 /* Description: Enable interrupt */
5370 /* Description: Disable interrupt */
5422 /* Description: PWM module enable register */
5431 /* Description: Selects operating mode of the wave counter */
5440 /* Description: Value up to which the pulse generator counter counts */
5447 /* Description: Configuration for PWM_CLK */
5462 /* Description: Configuration of the decoder */
5479 /* Description: Number of playbacks of a loop */
5487 /* Description: Description cluster[n]: Beginning address in RAM of this sequence */
5494 /* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */
5502 /* Description: Description cluster[n]: Number of additional PWM periods between samples loaded int…
5510 /* Description: Description cluster[n]: Time added after the sequence */
5517 /* Description: Description collection[n]: Output pin select for PWM channel n */
5531 /* Description: Quadrature Decoder */
5534 /* Description: Task starting the quadrature decoder */
5541 /* Description: Task stopping the quadrature decoder */
5548 /* Description: Read and clear ACC and ACCDBL */
5555 /* Description: Read and clear ACC */
5562 /* Description: Read and clear ACCDBL */
5569 /* Description: Event being generated for every new sample value written to the SAMPLE register */
5576 /* Description: Non-null report ready */
5583 /* Description: ACC or ACCDBL register overflow */
5590 /* Description: Double displacement(s) detected */
5597 /* Description: QDEC has been stopped */
5604 /* Description: Shortcut register */
5649 /* Description: Enable interrupt */
5687 /* Description: Disable interrupt */
5725 /* Description: Enable the quadrature decoder */
5734 /* Description: LED output pin polarity */
5743 /* Description: Sample period */
5761 /* Description: Motion sample value */
5768 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
5784 /* Description: Register accumulating the valid transitions */
5791 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
5798 /* Description: Pin select for LED signal */
5811 /* Description: Pin select for A signal */
5824 /* Description: Pin select for B signal */
5837 /* Description: Enable input debounce filters */
5846 /* Description: Time period the LED is switched ON prior to sampling */
5853 /* Description: Register accumulating the number of detected double transitions */
5860 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
5868 /* Description: 2.4 GHz Radio */
5871 /* Description: Enable RADIO in TX mode */
5878 /* Description: Enable RADIO in RX mode */
5885 /* Description: Start RADIO */
5892 /* Description: Stop RADIO */
5899 /* Description: Disable RADIO */
5906 /* Description: Start the RSSI and take one single sample of the receive signal strength. */
5913 /* Description: Stop the RSSI measurement */
5920 /* Description: Start the bit counter */
5927 /* Description: Stop the bit counter */
5934 /* Description: RADIO has ramped up and is ready to be started */
5941 /* Description: Address sent or received */
5948 /* Description: Packet payload sent or received */
5955 /* Description: Packet sent or received */
5962 /* Description: RADIO has been disabled */
5969 /* Description: A device address match occurred on the last received packet */
5976 /* Description: No device address match occurred on the last received packet */
5983 /* Description: Sampling of receive signal strength complete. */
5990 /* Description: Bit counter reached bit count value. */
5997 /* Description: Packet received with CRC ok */
6004 /* Description: Packet received with CRC error */
6011 /* Description: Shortcut register */
6062 /* Description: Enable interrupt */
6142 /* Description: Disable interrupt */
6222 /* Description: CRC status */
6231 /* Description: Received address */
6238 /* Description: CRC field of previously received packet */
6245 /* Description: Device address match index */
6252 /* Description: Packet pointer */
6259 /* Description: Frequency */
6272 /* Description: Output power */
6289 /* Description: Data rate and modulation */
6300 /* Description: Packet configuration register 0 */
6327 /* Description: Packet configuration register 1 */
6354 /* Description: Base address 0 */
6361 /* Description: Base address 1 */
6368 /* Description: Prefixes bytes for logical addresses 0-3 */
6387 /* Description: Prefixes bytes for logical addresses 4-7 */
6406 /* Description: Transmit address select */
6413 /* Description: Receive address select */
6464 /* Description: CRC configuration */
6481 /* Description: CRC polynomial */
6488 /* Description: CRC initial value */
6495 /* Description: Inter Frame Spacing in us */
6502 /* Description: RSSI sample */
6509 /* Description: Current radio state */
6525 /* Description: Data whitening initial value */
6532 /* Description: Bit counter compare */
6539 /* Description: Description collection[n]: Device address base segment n */
6546 /* Description: Description collection[n]: Device address prefix n */
6553 /* Description: Device address match configuration */
6636 /* Description: Radio mode configuration register 0 */
6652 /* Description: Peripheral power control */
6662 /* Description: Random Number Generator */
6665 /* Description: Task starting the random number generator */
6672 /* Description: Task stopping the random number generator */
6679 /* Description: Event being generated for every new random number written to the VALUE register */
6686 /* Description: Shortcut register */
6695 /* Description: Enable interrupt */
6705 /* Description: Disable interrupt */
6715 /* Description: Configuration register */
6724 /* Description: Output random number */
6732 /* Description: Real time counter 0 */
6735 /* Description: Start RTC COUNTER */
6742 /* Description: Stop RTC COUNTER */
6749 /* Description: Clear RTC COUNTER */
6756 /* Description: Set COUNTER to 0xFFFFF0 */
6763 /* Description: Event on COUNTER increment */
6770 /* Description: Event on COUNTER overflow */
6777 /* Description: Description collection[n]: Compare event on CC[n] match */
6784 /* Description: Enable interrupt */
6829 /* Description: Disable interrupt */
6874 /* Description: Enable or disable event routing */
6913 /* Description: Enable event routing */
6958 /* Description: Disable event routing */
7003 /* Description: Current COUNTER value */
7010 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when R…
7017 /* Description: Description collection[n]: Compare register n */
7025 /* Description: Analog to Digital Converter */
7028 /* Description: Start the ADC and prepare the result buffer in RAM */
7035 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
7042 /* Description: Stop the ADC and terminate any on-going conversion */
7049 /* Description: Starts offset auto-calibration */
7056 /* Description: The ADC has started */
7063 /* Description: The ADC has filled up the Result buffer */
7070 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions m…
7077 /* Description: A result is ready to get transferred to RAM. */
7084 /* Description: Calibration is complete */
7091 /* Description: The ADC has stopped */
7098 /* Description: Description cluster[n]: Last results is equal or above CH[n].LIMIT.HIGH */
7105 /* Description: Description cluster[n]: Last results is equal or below CH[n].LIMIT.LOW */
7112 /* Description: Enable or disable interrupt */
7247 /* Description: Enable interrupt */
7404 /* Description: Disable interrupt */
7561 /* Description: Status */
7570 /* Description: Enable or disable ADC */
7579 /* Description: Description cluster[n]: Input positive pin selection for CH[n] */
7596 /* Description: Description cluster[n]: Input negative pin selection for CH[n] */
7613 /* Description: Description cluster[n]: Input configuration for CH[n] */
7672 /* Description: Description cluster[n]: High/low limits for event monitoring a channel */
7683 /* Description: Resolution configuration */
7694 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLU…
7710 /* Description: Controls normal or continuous sample rate */
7723 /* Description: Data pointer */
7730 /* Description: Maximum number of buffer words to transfer */
7737 /* Description: Number of buffer words transferred since last START */
7745 /* Description: Serial Peripheral Interface Master with EasyDMA */
7748 /* Description: Start SPI transaction */
7755 /* Description: Stop SPI transaction */
7762 /* Description: Suspend SPI transaction */
7769 /* Description: Resume SPI transaction */
7776 /* Description: SPI transaction has stopped */
7783 /* Description: End of RXD buffer reached */
7790 /* Description: End of RXD buffer and TXD buffer reached */
7797 /* Description: End of TXD buffer reached */
7804 /* Description: Transaction started */
7811 /* Description: Shortcut register */
7820 /* Description: Enable interrupt */
7858 /* Description: Disable interrupt */
7896 /* Description: Enable SPIM */
7905 /* Description: Pin select for SCK */
7918 /* Description: Pin select for MOSI signal */
7931 /* Description: Pin select for MISO signal */
7944 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
7958 /* Description: Data pointer */
7965 /* Description: Maximum number of bytes in receive buffer */
7972 /* Description: Number of bytes transferred in the last transaction */
7979 /* Description: EasyDMA list type */
7988 /* Description: Data pointer */
7995 /* Description: Maximum number of bytes in transmit buffer */
8002 /* Description: Number of bytes transferred in the last transaction */
8009 /* Description: EasyDMA list type */
8018 /* Description: Configuration register */
8039 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer.…
8047 /* Description: SPI Slave */
8050 /* Description: Acquire SPI semaphore */
8057 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
8064 /* Description: Granted transaction completed */
8071 /* Description: End of RXD buffer reached */
8078 /* Description: Semaphore acquired */
8085 /* Description: Shortcut register */
8094 /* Description: Enable interrupt */
8118 /* Description: Disable interrupt */
8142 /* Description: Semaphore status register */
8153 /* Description: Status from last transaction */
8170 /* Description: Enable SPI slave */
8179 /* Description: Pin select for SCK */
8192 /* Description: Pin select for MISO signal */
8205 /* Description: Pin select for MOSI signal */
8218 /* Description: Pin select for CSN signal */
8231 /* Description: RXD data pointer */
8238 /* Description: Maximum number of bytes in receive buffer */
8245 /* Description: Number of bytes received in last granted transaction */
8252 /* Description: TXD data pointer */
8259 /* Description: Maximum number of bytes in transmit buffer */
8266 /* Description: Number of bytes transmitted in last granted transaction */
8273 /* Description: Configuration register */
8294 /* Description: Default character. Character clocked out in case of an ignored transaction. */
8301 /* Description: Over-read character */
8309 /* Description: Temperature Sensor */
8312 /* Description: Start temperature measurement */
8319 /* Description: Stop temperature measurement */
8326 /* Description: Temperature measurement complete, data ready */
8333 /* Description: Enable interrupt */
8343 /* Description: Disable interrupt */
8353 /* Description: Temperature in degC (0.25deg steps) */
8360 /* Description: Slope of 1st piece wise linear function */
8367 /* Description: Slope of 2nd piece wise linear function */
8374 /* Description: Slope of 3rd piece wise linear function */
8381 /* Description: Slope of 4th piece wise linear function */
8388 /* Description: Slope of 5th piece wise linear function */
8395 /* Description: Slope of 6th piece wise linear function */
8402 /* Description: y-intercept of 1st piece wise linear function */
8409 /* Description: y-intercept of 2nd piece wise linear function */
8416 /* Description: y-intercept of 3rd piece wise linear function */
8423 /* Description: y-intercept of 4th piece wise linear function */
8430 /* Description: y-intercept of 5th piece wise linear function */
8437 /* Description: y-intercept of 6th piece wise linear function */
8444 /* Description: End point of 1st piece wise linear function */
8451 /* Description: End point of 2nd piece wise linear function */
8458 /* Description: End point of 3rd piece wise linear function */
8465 /* Description: End point of 4th piece wise linear function */
8472 /* Description: End point of 5th piece wise linear function */
8480 /* Description: Timer/Counter 0 */
8483 /* Description: Start Timer */
8490 /* Description: Stop Timer */
8497 /* Description: Increment Timer (Counter mode only) */
8504 /* Description: Clear time */
8511 /* Description: Deprecated register - Shut down timer */
8518 /* Description: Description collection[n]: Capture Timer value to CC[n] register */
8525 /* Description: Description collection[n]: Compare event on CC[n] match */
8532 /* Description: Shortcut register */
8607 /* Description: Enable interrupt */
8652 /* Description: Disable interrupt */
8697 /* Description: Timer mode selection */
8707 /* Description: Configure the number of bits used by the TIMER */
8718 /* Description: Timer prescaler register */
8725 /* Description: Description collection[n]: Capture/Compare register n */
8733 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA */
8736 /* Description: Start TWI receive sequence */
8743 /* Description: Start TWI transmit sequence */
8750 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
8757 /* Description: Suspend TWI transaction */
8764 /* Description: Resume TWI transaction */
8771 /* Description: TWI stopped */
8778 /* Description: TWI error */
8785 /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is …
8792 /* Description: Receive sequence started */
8799 /* Description: Transmit sequence started */
8806 /* Description: Byte boundary, starting to receive the last byte */
8813 /* Description: Byte boundary, starting to transmit the last byte */
8820 /* Description: Shortcut register */
8859 /* Description: Enable or disable interrupt */
8904 /* Description: Enable interrupt */
8956 /* Description: Disable interrupt */
9008 /* Description: Error source */
9029 /* Description: Enable TWIM */
9038 /* Description: Pin select for SCL signal */
9051 /* Description: Pin select for SDA signal */
9064 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
9074 /* Description: Data pointer */
9081 /* Description: Maximum number of bytes in receive buffer */
9088 /* Description: Number of bytes transferred in the last transaction */
9095 /* Description: EasyDMA list type */
9104 /* Description: Data pointer */
9111 /* Description: Maximum number of bytes in transmit buffer */
9118 /* Description: Number of bytes transferred in the last transaction */
9125 /* Description: EasyDMA list type */
9134 /* Description: Address used in the TWI transfer */
9142 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */
9145 /* Description: Stop TWI transaction */
9152 /* Description: Suspend TWI transaction */
9159 /* Description: Resume TWI transaction */
9166 /* Description: Prepare the TWI slave to respond to a write command */
9173 /* Description: Prepare the TWI slave to respond to a read command */
9180 /* Description: TWI stopped */
9187 /* Description: TWI error */
9194 /* Description: Receive sequence started */
9201 /* Description: Transmit sequence started */
9208 /* Description: Write command received */
9215 /* Description: Read command received */
9222 /* Description: Shortcut register */
9237 /* Description: Enable or disable interrupt */
9276 /* Description: Enable interrupt */
9321 /* Description: Disable interrupt */
9366 /* Description: Error source */
9387 /* Description: Status register indicating which address had a match */
9394 /* Description: Enable TWIS */
9403 /* Description: Pin select for SCL signal */
9416 /* Description: Pin select for SDA signal */
9429 /* Description: RXD Data pointer */
9436 /* Description: Maximum number of bytes in RXD buffer */
9443 /* Description: Number of bytes transferred in the last RXD transaction */
9450 /* Description: TXD Data pointer */
9457 /* Description: Maximum number of bytes in TXD buffer */
9464 /* Description: Number of bytes transferred in the last TXD transaction */
9471 /* Description: Description collection[n]: TWI slave address n */
9478 /* Description: Configuration register for the address match mechanism */
9493 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
9501 /* Description: UART with EasyDMA */
9504 /* Description: Start UART receiver */
9511 /* Description: Stop UART receiver */
9518 /* Description: Start UART transmitter */
9525 /* Description: Stop UART transmitter */
9532 /* Description: Flush RX FIFO into RX buffer */
9539 /* Description: CTS is activated (set low). Clear To Send. */
9546 /* Description: CTS is deactivated (set high). Not Clear To Send. */
9553 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
9560 /* Description: Receive buffer is filled up */
9567 /* Description: Data sent from TXD */
9574 /* Description: Last TX byte transmitted */
9581 /* Description: Error detected */
9588 /* Description: Receiver timeout */
9595 /* Description: UART receiver has started */
9602 /* Description: UART transmitter has started */
9609 /* Description: Transmitter stopped */
9616 /* Description: Shortcut register */
9631 /* Description: Enable or disable interrupt */
9700 /* Description: Enable interrupt */
9780 /* Description: Disable interrupt */
9860 /* Description: Error source Note : this register is read / write one to clear. */
9887 /* Description: Enable UART */
9896 /* Description: Pin select for RTS signal */
9909 /* Description: Pin select for TXD signal */
9922 /* Description: Pin select for CTS signal */
9935 /* Description: Pin select for RXD signal */
9948 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
9973 /* Description: Data pointer */
9980 /* Description: Maximum number of bytes in receive buffer */
9987 /* Description: Number of bytes transferred in the last transaction */
9994 /* Description: Data pointer */
10001 /* Description: Maximum number of bytes in transmit buffer */
10008 /* Description: Number of bytes transferred in the last transaction */
10015 /* Description: Configuration of parity and hardware flow control */
10037 /* Description: User information configuration registers */
10040 /* Description: Description collection[n]: Reserved for Nordic firmware design */
10047 /* Description: Description collection[n]: Reserved for Nordic hardware design */
10054 /* Description: Description collection[n]: Reserved for customer */
10061 /* Description: Description collection[n]: Mapping of the nRESET function (see POWER chapter for de…
10074 /* Description: Access port protection */
10084 /* Description: Watchdog Timer */
10087 /* Description: Start the watchdog */
10094 /* Description: Watchdog timeout */
10101 /* Description: Enable interrupt */
10111 /* Description: Disable interrupt */
10121 /* Description: Run status */
10130 /* Description: Request status */
10181 /* Description: Counter reload value */
10188 /* Description: Enable register for reload request registers */
10239 /* Description: Configuration register */
10254 /* Description: Description collection[n]: Reload request n */