Lines Matching full:enable

42 /* Description: Interrupt enable set register. */
44 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
49 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
51 /* Bit 1 : Enable interrupt on RESOLVED event. */
56 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
58 /* Bit 0 : Enable interrupt on END event. */
63 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
66 /* Description: Interrupt enable clear register. */
97 /* Description: Enable AAR. */
99 /* Bits 1..0 : Enable AAR. */
100 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
101 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
103 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
126 /* Description: Interrupt enable set register. */
128 /* Bit 0 : Enable interrupt on END event. */
133 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
136 /* Description: Interrupt enable clear register. */
155 /* Description: ADC enable. */
157 /* Bits 1..0 : ADC enable. */
158 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
159 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
240 /* Description: Interrupt enable set register. */
242 /* Bit 2 : Enable interrupt on ERROR event. */
247 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
249 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
254 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
256 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
261 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
264 /* Description: Interrupt enable clear register. */
297 /* Description: CCM enable. */
299 /* Bits 1..0 : CCM enable. */
300 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
301 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
328 /* Description: Interrupt enable set register. */
330 /* Bit 4 : Enable interrupt on CTTO event. */
335 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
337 /* Bit 3 : Enable interrupt on DONE event. */
342 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
344 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
349 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
351 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
356 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
359 /* Description: Interrupt enable clear register. */
479 /* Description: Interrupt enable set register. */
481 /* Bit 1 : Enable interrupt on ERRORECB event. */
486 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
488 /* Bit 0 : Enable interrupt on ENDECB event. */
493 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
496 /* Description: Interrupt enable clear register. */
555 /* Description: Radio calibration override enable. */
2112 /* Description: Interrupt enable set register. */
2114 /* Bit 31 : Enable interrupt on PORT event. */
2119 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
2121 /* Bit 3 : Enable interrupt on IN[3] event. */
2126 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
2128 /* Bit 2 : Enable interrupt on IN[2] event. */
2133 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
2135 /* Bit 1 : Enable interrupt on IN[1] event. */
2140 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
2142 /* Bit 0 : Enable interrupt on IN[0] event. */
2147 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
2150 /* Description: Interrupt enable clear register. */
2262 /* Description: Interrupt enable set register. */
2264 /* Bit 3 : Enable interrupt on CROSS event. */
2269 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
2271 /* Bit 2 : Enable interrupt on UP event. */
2276 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
2278 /* Bit 1 : Enable interrupt on DOWN event. */
2283 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
2285 /* Bit 0 : Enable interrupt on READY event. */
2290 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
2293 /* Description: Interrupt enable clear register. */
2333 /* Description: Enable the LPCOMP. */
2335 /* Bits 1..0 : Enable or disable LPCOMP. */
2336 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2337 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.…
2339 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
2533 /* Description: Erase and write protection bit enable set register. */
2535 /* Bit 31 : Protection enable for region 31. */
2540 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
2542 /* Bit 30 : Protection enable for region 30. */
2547 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
2549 /* Bit 29 : Protection enable for region 29. */
2554 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
2556 /* Bit 28 : Protection enable for region 28. */
2561 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
2563 /* Bit 27 : Protection enable for region 27. */
2568 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
2570 /* Bit 26 : Protection enable for region 26. */
2575 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
2577 /* Bit 25 : Protection enable for region 25. */
2582 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
2584 /* Bit 24 : Protection enable for region 24. */
2589 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
2591 /* Bit 23 : Protection enable for region 23. */
2596 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
2598 /* Bit 22 : Protection enable for region 22. */
2603 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
2605 /* Bit 21 : Protection enable for region 21. */
2610 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
2612 /* Bit 20 : Protection enable for region 20. */
2617 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
2619 /* Bit 19 : Protection enable for region 19. */
2624 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
2626 /* Bit 18 : Protection enable for region 18. */
2631 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
2633 /* Bit 17 : Protection enable for region 17. */
2638 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
2640 /* Bit 16 : Protection enable for region 16. */
2645 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
2647 /* Bit 15 : Protection enable for region 15. */
2652 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
2654 /* Bit 14 : Protection enable for region 14. */
2659 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
2661 /* Bit 13 : Protection enable for region 13. */
2666 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
2668 /* Bit 12 : Protection enable for region 12. */
2673 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
2675 /* Bit 11 : Protection enable for region 11. */
2680 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
2682 /* Bit 10 : Protection enable for region 10. */
2687 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
2689 /* Bit 9 : Protection enable for region 9. */
2694 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
2696 /* Bit 8 : Protection enable for region 8. */
2701 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
2703 /* Bit 7 : Protection enable for region 7. */
2708 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
2710 /* Bit 6 : Protection enable for region 6. */
2715 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
2717 /* Bit 5 : Protection enable for region 5. */
2722 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
2724 /* Bit 4 : Protection enable for region 4. */
2729 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
2731 /* Bit 3 : Protection enable for region 3. */
2736 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
2738 /* Bit 2 : Protection enable for region 2. */
2743 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
2745 /* Bit 1 : Protection enable for region 1. */
2750 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
2752 /* Bit 0 : Protection enable for region 0. */
2757 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
2760 /* Description: Erase and write protection bit enable set register. */
2762 /* Bit 31 : Protection enable for region 63. */
2767 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
2769 /* Bit 30 : Protection enable for region 62. */
2774 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
2776 /* Bit 29 : Protection enable for region 61. */
2781 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
2783 /* Bit 28 : Protection enable for region 60. */
2788 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
2790 /* Bit 27 : Protection enable for region 59. */
2795 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
2797 /* Bit 26 : Protection enable for region 58. */
2802 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
2804 /* Bit 25 : Protection enable for region 57. */
2809 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
2811 /* Bit 24 : Protection enable for region 56. */
2816 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
2818 /* Bit 23 : Protection enable for region 55. */
2823 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
2825 /* Bit 22 : Protection enable for region 54. */
2830 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
2832 /* Bit 21 : Protection enable for region 53. */
2837 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
2839 /* Bit 20 : Protection enable for region 52. */
2844 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
2846 /* Bit 19 : Protection enable for region 51. */
2851 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
2853 /* Bit 18 : Protection enable for region 50. */
2858 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
2860 /* Bit 17 : Protection enable for region 49. */
2865 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
2867 /* Bit 16 : Protection enable for region 48. */
2872 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
2874 /* Bit 15 : Protection enable for region 47. */
2879 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
2881 /* Bit 14 : Protection enable for region 46. */
2886 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
2888 /* Bit 13 : Protection enable for region 45. */
2893 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
2895 /* Bit 12 : Protection enable for region 44. */
2900 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
2902 /* Bit 11 : Protection enable for region 43. */
2907 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
2909 /* Bit 10 : Protection enable for region 42. */
2914 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
2916 /* Bit 9 : Protection enable for region 41. */
2921 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
2923 /* Bit 8 : Protection enable for region 40. */
2928 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
2930 /* Bit 7 : Protection enable for region 39. */
2935 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
2937 /* Bit 6 : Protection enable for region 38. */
2942 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
2944 /* Bit 5 : Protection enable for region 37. */
2949 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
2951 /* Bit 4 : Protection enable for region 36. */
2956 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
2958 /* Bit 3 : Protection enable for region 35. */
2963 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
2965 /* Bit 2 : Protection enable for region 34. */
2970 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
2972 /* Bit 1 : Protection enable for region 33. */
2977 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
2979 /* Bit 0 : Protection enable for region 32. */
2984 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
3019 /* Bits 1..0 : Program write enable. */
3049 /* Description: Interrupt enable set register. */
3051 /* Bit 2 : Enable interrupt on POFWARN event. */
3056 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
3059 /* Description: Interrupt enable clear register. */
3159 /* Bit 0 : Power failure comparator enable. */
3202 /* Bit 0 : Enable or disable pin reset in debug interface mode. */
3236 /* Description: DCDC converter enable configuration register. */
3238 /* Bit 0 : Enable DCDC converter. */
3264 /* Description: Channel enable. */
3266 /* Bit 31 : Enable PPI channel 31. */
3272 /* Bit 30 : Enable PPI channel 30. */
3278 /* Bit 29 : Enable PPI channel 29. */
3284 /* Bit 28 : Enable PPI channel 28. */
3290 /* Bit 27 : Enable PPI channel 27. */
3296 /* Bit 26 : Enable PPI channel 26. */
3302 /* Bit 25 : Enable PPI channel 25. */
3308 /* Bit 24 : Enable PPI channel 24. */
3314 /* Bit 23 : Enable PPI channel 23. */
3320 /* Bit 22 : Enable PPI channel 22. */
3326 /* Bit 21 : Enable PPI channel 21. */
3332 /* Bit 20 : Enable PPI channel 20. */
3338 /* Bit 15 : Enable PPI channel 15. */
3344 /* Bit 14 : Enable PPI channel 14. */
3350 /* Bit 13 : Enable PPI channel 13. */
3356 /* Bit 12 : Enable PPI channel 12. */
3362 /* Bit 11 : Enable PPI channel 11. */
3368 /* Bit 10 : Enable PPI channel 10. */
3374 /* Bit 9 : Enable PPI channel 9. */
3380 /* Bit 8 : Enable PPI channel 8. */
3386 /* Bit 7 : Enable PPI channel 7. */
3392 /* Bit 6 : Enable PPI channel 6. */
3398 /* Bit 5 : Enable PPI channel 5. */
3404 /* Bit 4 : Enable PPI channel 4. */
3410 /* Bit 3 : Enable PPI channel 3. */
3416 /* Bit 2 : Enable PPI channel 2. */
3422 /* Bit 1 : Enable PPI channel 1. */
3428 /* Bit 0 : Enable PPI channel 0. */
3435 /* Description: Channel enable set. */
3437 /* Bit 31 : Enable PPI channel 31. */
3442 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
3444 /* Bit 30 : Enable PPI channel 30. */
3449 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
3451 /* Bit 29 : Enable PPI channel 29. */
3456 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
3458 /* Bit 28 : Enable PPI channel 28. */
3463 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
3465 /* Bit 27 : Enable PPI channel 27. */
3470 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
3472 /* Bit 26 : Enable PPI channel 26. */
3477 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
3479 /* Bit 25 : Enable PPI channel 25. */
3484 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
3486 /* Bit 24 : Enable PPI channel 24. */
3491 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
3493 /* Bit 23 : Enable PPI channel 23. */
3498 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
3500 /* Bit 22 : Enable PPI channel 22. */
3505 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
3507 /* Bit 21 : Enable PPI channel 21. */
3512 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
3514 /* Bit 20 : Enable PPI channel 20. */
3519 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
3521 /* Bit 15 : Enable PPI channel 15. */
3526 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
3528 /* Bit 14 : Enable PPI channel 14. */
3533 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
3535 /* Bit 13 : Enable PPI channel 13. */
3540 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
3542 /* Bit 12 : Enable PPI channel 12. */
3547 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
3549 /* Bit 11 : Enable PPI channel 11. */
3554 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
3556 /* Bit 10 : Enable PPI channel 10. */
3561 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
3563 /* Bit 9 : Enable PPI channel 9. */
3568 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
3570 /* Bit 8 : Enable PPI channel 8. */
3575 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
3577 /* Bit 7 : Enable PPI channel 7. */
3582 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
3584 /* Bit 6 : Enable PPI channel 6. */
3589 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
3591 /* Bit 5 : Enable PPI channel 5. */
3596 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
3598 /* Bit 4 : Enable PPI channel 4. */
3603 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
3605 /* Bit 3 : Enable PPI channel 3. */
3610 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
3612 /* Bit 2 : Enable PPI channel 2. */
3617 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
3619 /* Bit 1 : Enable PPI channel 1. */
3624 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
3626 /* Bit 0 : Enable PPI channel 0. */
3631 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
3634 /* Description: Channel enable clear. */
4023 /* Description: Interrupt enable set register. */
4025 /* Bit 2 : Enable interrupt on ACCOF event. */
4030 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
4032 /* Bit 1 : Enable interrupt on REPORTRDY event. */
4037 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
4039 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
4044 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
4047 /* Description: Interrupt enable clear register. */
4071 /* Description: Enable the QDEC. */
4073 /* Bit 0 : Enable or disable QDEC. */
4074 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
4075 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
4077 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
4126 /* Description: Enable debouncer input filters. */
4128 /* Bit 0 : Enable debounce input filters. */
4220 /* Description: Interrupt enable set register. */
4222 /* Bit 10 : Enable interrupt on BCMATCH event. */
4227 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
4229 /* Bit 7 : Enable interrupt on RSSIEND event. */
4234 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
4236 /* Bit 6 : Enable interrupt on DEVMISS event. */
4241 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
4243 /* Bit 5 : Enable interrupt on DEVMATCH event. */
4248 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
4250 /* Bit 4 : Enable interrupt on DISABLED event. */
4255 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
4257 /* Bit 3 : Enable interrupt on END event. */
4262 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
4264 /* Bit 2 : Enable interrupt on PAYLOAD event. */
4269 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
4271 /* Bit 1 : Enable interrupt on ADDRESS event. */
4276 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
4278 /* Bit 0 : Enable interrupt on READY event. */
4283 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
4286 /* Description: Interrupt enable clear register. */
4432 /* Bit 25 : Packet whitening enable. */
4504 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
4510 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
4516 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
4522 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
4528 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
4534 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
4540 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
4546 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
4584 /* Description: Test features enable register. */
4677 /* Bit 7 : Enable or disable device address matching using device address 7. */
4683 /* Bit 6 : Enable or disable device address matching using device address 6. */
4689 /* Bit 5 : Enable or disable device address matching using device address 5. */
4695 /* Bit 4 : Enable or disable device address matching using device address 4. */
4701 /* Bit 3 : Enable or disable device address matching using device address 3. */
4707 /* Bit 2 : Enable or disable device address matching using device address 2. */
4713 /* Bit 1 : Enable or disable device address matching using device address 1. */
4719 /* Bit 0 : Enable or disable device address matching using device address 0. */
4756 /* Bit 31 : Enable or disable override of default trim values. */
4757 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
4758 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE fi…
4789 /* Description: Interrupt enable set register */
4791 /* Bit 0 : Enable interrupt on VALRDY event. */
4796 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
4799 /* Description: Interrupt enable clear register */
4811 /* Bit 0 : Digital error correction enable. */
4838 /* Description: Interrupt enable set register. */
4840 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
4845 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
4847 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
4852 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
4854 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
4859 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
4861 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
4866 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
4868 /* Bit 1 : Enable interrupt on OVRFLW event. */
4873 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
4875 /* Bit 0 : Enable interrupt on TICK event. */
4880 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
4883 /* Description: Interrupt enable clear register. */
4928 /* Description: Configures event enable routing to PPI for each RTC event. */
4930 /* Bit 19 : COMPARE[3] event enable. */
4936 /* Bit 18 : COMPARE[2] event enable. */
4942 /* Bit 17 : COMPARE[1] event enable. */
4948 /* Bit 16 : COMPARE[0] event enable. */
4954 /* Bit 1 : OVRFLW event enable. */
4960 /* Bit 0 : TICK event enable. */
4967 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN…
4969 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
4974 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
4976 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
4981 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
4983 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
4988 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
4990 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
4995 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
4997 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
5002 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
5004 /* Bit 0 : Enable routing to PPI of TICK event. */
5009 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
5091 /* Description: Interrupt enable set register. */
5093 /* Bit 2 : Enable interrupt on READY event. */
5098 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
5101 /* Description: Interrupt enable clear register. */
5111 /* Description: Enable SPI. */
5113 /* Bits 2..0 : Enable or disable SPI. */
5114 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5115 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5117 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
5191 /* Description: Interrupt enable set register. */
5193 /* Bit 10 : Enable interrupt on ACQUIRED event. */
5198 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
5200 /* Bit 4 : enable interrupt on ENDRX event. */
5205 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
5207 /* Bit 1 : Enable interrupt on END event. */
5212 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
5215 /* Description: Interrupt enable clear register. */
5267 /* Description: Enable SPIS. */
5269 /* Bits 2..0 : Enable or disable SPIS. */
5270 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5271 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5273 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
5352 /* Description: Interrupt enable set register. */
5354 /* Bit 0 : Enable interrupt on DATARDY event. */
5359 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
5362 /* Description: Interrupt enable clear register. */
5436 /* Description: Interrupt enable set register. */
5438 /* Bit 19 : Enable interrupt on COMPARE[3] */
5443 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
5445 /* Bit 18 : Enable interrupt on COMPARE[2] */
5450 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
5452 /* Bit 17 : Enable interrupt on COMPARE[1] */
5457 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
5459 /* Bit 16 : Enable interrupt on COMPARE[0] */
5464 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
5467 /* Description: Interrupt enable clear register. */
5553 /* Description: Interrupt enable set register. */
5555 /* Bit 18 : Enable interrupt on SUSPENDED event. */
5560 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
5562 /* Bit 14 : Enable interrupt on BB event. */
5567 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
5569 /* Bit 9 : Enable interrupt on ERROR event. */
5574 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
5576 /* Bit 7 : Enable interrupt on TXDSENT event. */
5581 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
5583 /* Bit 2 : Enable interrupt on READY event. */
5588 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
5590 /* Bit 1 : Enable interrupt on STOPPED event. */
5595 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
5598 /* Description: Interrupt enable clear register. */
5667 /* Description: Enable two-wire master. */
5669 /* Bits 2..0 : Enable or disable W2M */
5670 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5671 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5735 /* Description: Interrupt enable set register. */
5737 /* Bit 17 : Enable interrupt on RXTO event. */
5742 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
5744 /* Bit 9 : Enable interrupt on ERROR event. */
5749 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
5751 /* Bit 7 : Enable interrupt on TXRDY event. */
5756 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
5758 /* Bit 2 : Enable interrupt on RXRDY event. */
5763 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
5765 /* Bit 1 : Enable interrupt on NCTS event. */
5770 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
5772 /* Bit 0 : Enable interrupt on CTS event. */
5777 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
5780 /* Description: Interrupt enable clear register. */
5856 /* Description: Enable UART and acquire IOs. */
5858 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
5859 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5860 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5967 /* Description: Interrupt enable set register. */
5969 /* Bit 0 : Enable interrupt on TIMEOUT event. */
5974 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
5977 /* Description: Interrupt enable clear register. */
6047 /* Description: Reload request enable. */
6049 /* Bit 7 : Enable or disable RR[7] register. */
6055 /* Bit 6 : Enable or disable RR[6] register. */
6061 /* Bit 5 : Enable or disable RR[5] register. */
6067 /* Bit 4 : Enable or disable RR[4] register. */
6073 /* Bit 3 : Enable or disable RR[3] register. */
6079 /* Bit 2 : Enable or disable RR[2] register. */
6085 /* Bit 1 : Enable or disable RR[1] register. */
6091 /* Bit 0 : Enable or disable RR[0] register. */