Lines Matching full:in
5 * Redistribution and use in source and binary forms, with or without
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
89 * @param[in] p_reg Pointer to the peripheral registers structure.
90 * @param[in] event Event to clear.
98 * @param[in] p_reg Pointer to the peripheral registers structure.
99 * @param[in] event Event to check.
110 * @param[in] p_reg Pointer to the peripheral registers structure.
111 * @param[in] mask Interrupts to enable.
119 * @param[in] p_reg Pointer to the peripheral registers structure.
120 * @param[in] mask Interrupts to disable.
128 * @param[in] p_reg Pointer to the peripheral registers structure.
129 * @param[in] spu_int Interrupt to check.
140 * @param[in] p_reg Pointer to the peripheral registers structure.
141 * @param[in] event Event to configure.
142 * @param[in] channel Channel to connect with published event.
151 * @param[in] p_reg Pointer to the peripheral registers structure.
152 * @param[in] event Event to clear.
160 * @param[in] p_reg Pointer to the peripheral registers structure.
168 * @brief Function for configuring the DPPI channels to be available in particular domains.
170 * Channels are configured as bitmask. Set one in bitmask to make channels available only in secure
171 * domain. Set zero to make it available in secure and non-secure domains.
173 * @param[in] p_reg Pointer to the peripheral registers structure.
174 * @param[in] dppi_id DPPI peripheral id.
175 * @param[in] channels_mask Bitmask with channels configuration.
176 * @param[in] lock_conf Lock configuration until next SoC reset.
184 * @brief Function for configuring the GPIO pins to be available in particular domains.
186 * GPIO pins are configured as bitmask. Set one in bitmask to make particular pin available only
187 * in secure domain. Set zero to make it available in secure and non-secure domains.
189 * @param[in] p_reg Pointer to the peripheral registers structure.
190 * @param[in] gpio_port Port number.
191 * @param[in] gpio_mask Bitmask with gpio configuration.
192 * @param[in] lock_conf Lock configuration until next SoC reset.
202 * @param[in] p_reg Pointer to the peripheral registers structure.
203 * @param[in] flash_nsc_id Non-secure callable flash region ID.
204 * @param[in] flash_nsc_size Non-secure callable flash region size.
205 * @param[in] region_number Flash region number.
206 * @param[in] lock_conf Lock configuration until next SoC reset.
217 * @param[in] p_reg Pointer to the peripheral registers structure.
218 * @param[in] ram_nsc_id Non-secure callable RAM region ID.
219 * @param[in] ram_nsc_size Non-secure callable RAM region size.
220 * @param[in] region_number RAM region number.
221 * @param[in] lock_conf Lock configuration until next SoC reset.
234 * @param[in] p_reg Pointer to the peripheral registers structure.
235 * @param[in] region_id Flash region index.
236 * @param[in] secure_attr Set region attribute to secure.
237 * @param[in] permissions Flash region permissions.
238 * @param[in] lock_conf Lock configuration until next SoC reset.
251 * @param[in] p_reg Pointer to the peripheral registers structure.
252 * @param[in] region_id RAM region index.
253 * @param[in] secure_attr Set region attribute to secure.
254 * @param[in] permissions RAM region permissions.
255 * @param[in] lock_conf Lock configuration until next SoC reset.
266 * @param[in] p_reg Pointer to the peripheral registers structure.
267 * @param[in] peripheral_id ID number of a particular peripheral.
268 * @param[in] secure_attr Peripheral registers accessible only from secure domain.
269 * @param[in] secure_dma DMA transfers possible only from RAM memory in secure domain.
270 * @param[in] lock_conf Lock configuration until next SoC reset.