Lines Matching +full:0 +full:- +full:5
4 "Counter": "0,1,2,3,4,5,6,7",
7 "EventCode": "0xb0",
10 "UMask": "0x9",
15 "Counter": "0,1,2,3,4,5,6,7",
17 "EventCode": "0xb0",
19 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
21 "UMask": "0x9",
26 "Counter": "0,1,2,3,4,5,6,7",
29 "EventCode": "0xb0",
32 "UMask": "0x1",
37 "Counter": "0,1,2,3,4,5,6,7",
39 "EventCode": "0xb0",
42 "UMask": "0x8",
47 "Counter": "0,1,2,3,4,5,6,7",
50 "EventCode": "0xb0",
53 "UMask": "0x8",
58 "Counter": "0,1,2,3,4,5,6,7",
59 "EventCode": "0xc1",
63 "UMask": "0x1b",
68 "Counter": "0,1,2,3,4,5",
69 "EventCode": "0xc4",
78 "Counter": "0,1,2,3,4,5,6,7",
79 "EventCode": "0xc4",
88 "Counter": "0,1,2,3,4,5",
90 "EventCode": "0xc4",
94 "UMask": "0xf9",
99 "Counter": "0,1,2,3,4,5",
100 "EventCode": "0xc4",
104 "UMask": "0x7e",
109 "Counter": "0,1,2,3,4,5,6,7",
110 "EventCode": "0xc4",
115 "UMask": "0x11",
120 "Counter": "0,1,2,3,4,5,6,7",
121 "EventCode": "0xc4",
126 "UMask": "0x10",
131 "Counter": "0,1,2,3,4,5",
132 "EventCode": "0xc4",
136 "UMask": "0xfe",
141 "Counter": "0,1,2,3,4,5,6,7",
142 "EventCode": "0xc4",
147 "UMask": "0x1",
152 "Counter": "0,1,2,3,4,5",
153 "EventCode": "0xc4",
157 "UMask": "0xbf",
162 "Counter": "0,1,2,3,4,5,6,7",
163 "EventCode": "0xc4",
168 "UMask": "0x40",
173 "Counter": "0,1,2,3,4,5",
174 "EventCode": "0xc4",
178 "UMask": "0xeb",
183 "Counter": "0,1,2,3,4,5,6,7",
184 "EventCode": "0xc4",
189 "UMask": "0x80",
194 "Counter": "0,1,2,3,4,5",
195 "EventCode": "0xc4",
199 "UMask": "0xfb",
204 "Counter": "0,1,2,3,4,5",
206 "EventCode": "0xc4",
210 "UMask": "0xfb",
215 "Counter": "0,1,2,3,4,5",
217 "EventCode": "0xc4",
221 "UMask": "0x7e",
226 "Counter": "0,1,2,3,4,5",
227 "EventCode": "0xc4",
231 "UMask": "0xf9",
236 "Counter": "0,1,2,3,4,5,6,7",
237 "EventCode": "0xc4",
242 "UMask": "0x2",
247 "Counter": "0,1,2,3,4,5",
248 "EventCode": "0xc4",
252 "UMask": "0xf7",
257 "Counter": "0,1,2,3,4,5,6,7",
258 "EventCode": "0xc4",
263 "UMask": "0x8",
268 "Counter": "0,1,2,3,4,5",
269 "EventCode": "0xc4",
273 "UMask": "0xc0",
278 "Counter": "0,1,2,3,4,5,6,7",
279 "EventCode": "0xc4",
284 "UMask": "0x20",
289 "Counter": "0,1,2,3,4,5",
291 "EventCode": "0xc4",
295 "UMask": "0xeb",
300 "Counter": "0,1,2,3,4,5",
301 "EventCode": "0xc4",
305 "UMask": "0xfd",
310 "Counter": "0,1,2,3,4,5",
312 "EventCode": "0xc4",
316 "UMask": "0xf7",
321 "Counter": "0,1,2,3,4,5",
323 "EventCode": "0xc4",
327 "UMask": "0xfe",
332 "Counter": "0,1,2,3,4,5",
333 "EventCode": "0xc5",
336 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
342 "Counter": "0,1,2,3,4,5,6,7",
343 "EventCode": "0xc5",
352 "Counter": "0,1,2,3,4,5",
353 "EventCode": "0xc5",
357 "UMask": "0x7e",
362 "Counter": "0,1,2,3,4,5,6,7",
363 "EventCode": "0xc5",
368 "UMask": "0x11",
372 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
373 "Counter": "0,1,2,3,4,5,6,7",
374 "EventCode": "0xc5",
379 "UMask": "0x10",
384 "Counter": "0,1,2,3,4,5",
385 "EventCode": "0xc5",
389 "UMask": "0xfe",
394 "Counter": "0,1,2,3,4,5,6,7",
395 "EventCode": "0xc5",
400 "UMask": "0x1",
405 "Counter": "0,1,2,3,4,5",
406 "EventCode": "0xc5",
410 "UMask": "0xeb",
414 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
415 "Counter": "0,1,2,3,4,5,6,7",
416 "EventCode": "0xc5",
419 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
421 "UMask": "0x80",
426 "Counter": "0,1,2,3,4,5",
427 "EventCode": "0xc5",
431 "UMask": "0xfb",
436 "Counter": "0,1,2,3,4,5,6,7",
437 "EventCode": "0xc5",
442 "UMask": "0x2",
447 "Counter": "0,1,2,3,4,5",
449 "EventCode": "0xc5",
453 "UMask": "0xfb",
458 "Counter": "0,1,2,3,4,5",
460 "EventCode": "0xc5",
464 "UMask": "0x7e",
469 "Counter": "0,1,2,3,4,5",
470 "EventCode": "0xc5",
474 "UMask": "0x80",
479 "Counter": "0,1,2,3,4,5,6,7",
480 "EventCode": "0xc5",
485 "UMask": "0x20",
490 "Counter": "0,1,2,3,4,5",
492 "EventCode": "0xc5",
496 "UMask": "0xeb",
501 "Counter": "0,1,2,3,4,5,6,7",
502 "EventCode": "0xc5",
505 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
507 "UMask": "0x8",
512 "Counter": "0,1,2,3,4,5",
513 "EventCode": "0xc5",
517 "UMask": "0xf7",
522 "Counter": "0,1,2,3,4,5",
524 "EventCode": "0xc5",
528 "UMask": "0xfe",
532 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
533 "Counter": "0,1,2,3,4,5,6,7",
534 "EventCode": "0xec",
536 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
538 "UMask": "0x10",
542 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
543 "Counter": "0,1,2,3,4,5,6,7",
544 "EventCode": "0xec",
546 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
548 "UMask": "0x20",
553 "Counter": "0,1,2,3,4,5,6,7",
554 "EventCode": "0xec",
558 "UMask": "0x70",
567 "UMask": "0x2",
572 "Counter": "0,1,2,3,4,5",
573 "EventCode": "0x3c",
581 "Counter": "0,1,2,3,4,5,6,7",
582 "EventCode": "0xec",
586 "UMask": "0x2",
591 "Counter": "0,1,2,3,4,5,6,7",
592 "EventCode": "0x3c",
596 "UMask": "0x2",
601 "Counter": "0,1,2,3,4,5,6,7",
602 "EventCode": "0xec",
605 "UMask": "0x40",
610 "Counter": "0,1,2,3,4,5,6,7",
613 "EventCode": "0xec",
616 "UMask": "0x40",
621 "Counter": "0,1,2,3,4,5,6,7",
622 "EventCode": "0x3c",
624 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
626 "UMask": "0x8",
635 "UMask": "0x3",
644 "UMask": "0x3",
649 "Counter": "0,1,2,3,4,5",
650 "EventCode": "0x3c",
654 "UMask": "0x1",
659 "Counter": "0,1,2,3,4,5,6,7",
660 "EventCode": "0x3c",
664 "UMask": "0x1",
673 "UMask": "0x2",
682 "UMask": "0x2",
687 "Counter": "0,1,2,3,4,5",
688 "EventCode": "0x3c",
696 "Counter": "0,1,2,3,4,5,6,7",
697 "EventCode": "0x3c",
705 "Counter": "0,1,2,3",
707 "EventCode": "0xa3",
710 "UMask": "0x8",
715 "Counter": "0,1,2,3",
717 "EventCode": "0xa3",
720 "UMask": "0x1",
725 "Counter": "0,1,2,3,4,5,6,7",
727 "EventCode": "0xa3",
730 "UMask": "0x10",
735 "Counter": "0,1,2,3",
737 "EventCode": "0xa3",
740 "UMask": "0xc",
745 "Counter": "0,1,2,3",
746 "CounterMask": "5",
747 "EventCode": "0xa3",
750 "UMask": "0x5",
755 "Counter": "0,1,2,3,4,5,6,7",
757 "EventCode": "0xa3",
760 "UMask": "0x4",
765 "Counter": "0,1,2,3,4,5,6,7",
766 "EventCode": "0xa6",
770 "UMask": "0x2",
775 "Counter": "0,1,2,3,4,5,6,7",
776 "EventCode": "0xa6",
779 "UMask": "0xc",
784 "Counter": "0,1,2,3,4,5,6,7",
785 "EventCode": "0xa6",
789 "UMask": "0x4",
794 "Counter": "0,1,2,3,4,5,6,7",
795 "EventCode": "0xa6",
799 "UMask": "0x8",
804 "Counter": "0,1,2,3,4,5,6,7",
805 "EventCode": "0xa6",
809 "UMask": "0x10",
814 "Counter": "0,1,2,3,4,5,6,7",
815 "CounterMask": "5",
816 "EventCode": "0xa6",
819 "UMask": "0x21",
824 "Counter": "0,1,2,3,4,5,6,7",
826 "EventCode": "0xa6",
830 "UMask": "0x40",
835 "Counter": "0,1,2,3,4,5,6,7",
836 "EventCode": "0xa6",
838 …"PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station …
840 "UMask": "0x80",
845 "Counter": "0,1,2,3",
846 "EventCode": "0x75",
850 "UMask": "0x1",
855 "Counter": "Fixed counter 0",
858 …uring hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
860 "UMask": "0x1",
864 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
865 "Counter": "Fixed counter 0",
868 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
870 "UMask": "0x1",
875 "Counter": "0,1,2,3,4,5",
876 "EventCode": "0xc0",
884 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
885 "Counter": "0,1,2,3,4,5,6,7",
886 "EventCode": "0xc0",
889 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
895 "Counter": "0,1,2,3,4,5,6,7",
896 "EventCode": "0xc0",
900 "UMask": "0x10",
905 "Counter": "0,1,2,3,4,5,6,7",
906 "EventCode": "0xc0",
911 "UMask": "0x2",
915 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
916 "Counter": "Fixed counter 0",
919 …red (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.",
921 "UMask": "0x1",
926 "Counter": "0,1,2,3,4,5,6,7",
927 "EventCode": "0xc0",
930 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
932 "UMask": "0x8",
937 "Counter": "0,1,2,3,4,5,6,7",
940 "EventCode": "0xad",
944 "UMask": "0x1",
949 "Counter": "0,1,2,3,4,5,6,7",
950 "EventCode": "0xad",
954 "UMask": "0x80",
959 "Counter": "0,1,2,3,4,5,6,7",
960 "EventCode": "0xad",
964 "UMask": "0x1",
969 "Counter": "0,1,2,3,4,5,6,7",
970 "EventCode": "0xad",
972 "MSRIndex": "0x3F7",
973 "MSRValue": "0x7",
975 "UMask": "0x40",
980 "Counter": "0,1,2,3,4,5,6,7",
981 "EventCode": "0xad",
983 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
985 "UMask": "0x10",
990 "Counter": "0,1,2,3,4,5,6,7",
991 "EventCode": "0xe7",
994 "UMask": "0x13",
999 "Counter": "0,1,2,3,4,5,6,7",
1000 "EventCode": "0xe7",
1003 "UMask": "0xac",
1007 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
1008 "Counter": "0,1,2,3,4,5,6,7",
1009 "EventCode": "0xe7",
1011 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
1013 "UMask": "0x3",
1017 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
1018 "Counter": "0,1,2,3,4,5,6,7",
1019 "EventCode": "0xe7",
1021 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
1023 "UMask": "0xc",
1028 "Counter": "0,1,2,3,4,5,6,7",
1029 "EventCode": "0xe7",
1032 "UMask": "0x80",
1037 "Counter": "0,1,2,3,4,5,6,7",
1038 "EventCode": "0xe7",
1041 "UMask": "0x40",
1046 "Counter": "0,1,2,3,4,5,6,7",
1047 "EventCode": "0xe7",
1050 "UMask": "0x10",
1055 "Counter": "0,1,2,3,4,5,6,7",
1056 "EventCode": "0xe7",
1059 "UMask": "0x20",
1064 "Counter": "0,1,2,3,4,5",
1066 "EventCode": "0x03",
1070 "UMask": "0x4",
1075 "Counter": "0,1,2,3,4,5",
1076 "EventCode": "0x03",
1080 "UMask": "0x4",
1085 "Counter": "0,1,2,3",
1086 "EventCode": "0x03",
1090 "UMask": "0x4",
1095 "Counter": "0,1,2,3,4,5",
1096 "EventCode": "0x03",
1100 "UMask": "0x1",
1105 "Counter": "0,1,2,3",
1106 "EventCode": "0x03",
1110 "UMask": "0x88",
1115 "Counter": "0,1,2,3",
1116 "EventCode": "0x03",
1120 "UMask": "0x82",
1125 "Counter": "0,1,2,3",
1126 "EventCode": "0x4c",
1128 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
1130 "UMask": "0x1",
1135 "Counter": "0,1,2,3,4,5,6,7",
1137 "EventCode": "0xa8",
1139 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
1141 "UMask": "0x1",
1146 "Counter": "0,1,2,3,4,5,6,7",
1148 "EventCode": "0xa8",
1150 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
1152 "UMask": "0x1",
1157 "Counter": "0,1,2,3,4,5,6,7",
1158 "EventCode": "0xa8",
1160 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
1162 "UMask": "0x1",
1167 "Counter": "0,1,2,3,4,5,6,7",
1170 "EventCode": "0xc3",
1174 "UMask": "0x1",
1179 "Counter": "0,1,2,3,4,5",
1180 "EventCode": "0xc3",
1183 "UMask": "0x8",
1188 "Counter": "0,1,2,3,4,5",
1189 "EventCode": "0xc3",
1192 "UMask": "0x80",
1196 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
1197 "Counter": "0,1,2,3,4,5",
1198 "EventCode": "0xc3",
1201 "UMask": "0x20",
1206 "Counter": "0,1,2,3,4,5",
1207 "EventCode": "0xc3",
1210 "UMask": "0x6f",
1215 "Counter": "0,1,2,3,4,5",
1216 "EventCode": "0xc3",
1219 "UMask": "0x1",
1223 "BriefDescription": "Self-modifying code (SMC) detected.",
1224 "Counter": "0,1,2,3,4,5,6,7",
1225 "EventCode": "0xc3",
1227 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
1229 "UMask": "0x4",
1234 "Counter": "0,1,2,3,4,5,6,7",
1235 "EventCode": "0xe0",
1239 "UMask": "0x20",
1244 "Counter": "0,1,2,3,4,5",
1245 "EventCode": "0xe4",
1250 "UMask": "0x1",
1255 "Counter": "0,1,2,3,4,5,6,7",
1256 "EventCode": "0xcc",
1260 "UMask": "0x20",
1265 "Counter": "0,1,2,3,4,5,6,7",
1266 "EventCode": "0xa2",
1268 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
1270 "UMask": "0x8",
1275 "Counter": "0,1,2,3,4,5,6,7",
1276 "EventCode": "0xa2",
1279 "UMask": "0x2",
1283 …ue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the fr…
1284 "Counter": "0,1,2,3,4,5",
1285 "EventCode": "0x75",
1287 …ue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the fr…
1289 "UMask": "0x2",
1293 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
1294 "Counter": "0,1,2,3,4,5,6,7",
1295 "EventCode": "0xa4",
1297 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
1299 "UMask": "0x2",
1304 "Counter": "0",
1305 "EventCode": "0xa4",
1307 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
1309 "UMask": "0x4",
1314 "Counter": "0",
1315 "EventCode": "0xa4",
1317 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
1319 "UMask": "0x8",
1324 "Counter": "0,1,2,3,4,5,6,7",
1325 "EventCode": "0xa4",
1328 "UMask": "0x10",
1332 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
1335 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
1337 "UMask": "0x4",
1341 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
1342 "Counter": "0,1,2,3,4,5,6,7",
1343 "EventCode": "0xa4",
1345 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
1347 "UMask": "0x1",
1352 "Counter": "0,1,2,3,4,5",
1353 "EventCode": "0x73",
1361 "Counter": "0,1,2,3,4,5",
1362 "EventCode": "0x73",
1365 "UMask": "0x2",
1370 "Counter": "0,1,2,3,4,5",
1371 "EventCode": "0x73",
1374 "UMask": "0x3",
1379 "Counter": "0,1,2,3,4,5",
1380 "EventCode": "0x73",
1383 "UMask": "0x4",
1388 "Counter": "0,1,2,3,4,5",
1389 "EventCode": "0x73",
1392 "UMask": "0x1",
1397 "Counter": "0,1,2,3,4,5",
1398 "EventCode": "0x74",
1405 "Counter": "0,1,2,3,4,5",
1406 "EventCode": "0x74",
1409 "UMask": "0x1",
1414 "Counter": "0,1,2,3,4,5",
1415 "EventCode": "0x74",
1418 "UMask": "0x2",
1423 "Counter": "0,1,2,3,4,5",
1424 "EventCode": "0x74",
1427 "UMask": "0x8",
1432 "Counter": "0,1,2,3,4,5",
1433 "EventCode": "0x74",
1436 "UMask": "0x20",
1441 "Counter": "0,1,2,3,4,5",
1442 "EventCode": "0x74",
1445 "UMask": "0x40",
1450 "Counter": "0,1,2,3,4,5",
1451 "EventCode": "0x74",
1454 "UMask": "0x10",
1459 "Counter": "0,1,2,3,4,5",
1460 "EventCode": "0x71",
1467 "Counter": "0,1,2,3,4,5",
1468 "EventCode": "0x71",
1472 "UMask": "0x2",
1477 "Counter": "0,1,2,3,4,5",
1478 "EventCode": "0x71",
1482 "UMask": "0x40",
1487 "Counter": "0,1,2,3,4,5",
1488 "EventCode": "0x71",
1491 "UMask": "0x1",
1496 "Counter": "0,1,2,3,4,5",
1497 "EventCode": "0x71",
1500 "UMask": "0x8",
1505 "Counter": "0,1,2,3,4,5",
1506 "EventCode": "0x71",
1509 "UMask": "0x8d",
1514 "Counter": "0,1,2,3,4,5",
1515 "EventCode": "0x71",
1518 "UMask": "0x72",
1523 "Counter": "0,1,2,3,4,5",
1524 "EventCode": "0x71",
1528 "UMask": "0x10",
1533 "Counter": "0,1,2,3,4,5",
1534 "EventCode": "0x71",
1537 "UMask": "0x80",
1542 "Counter": "0,1,2,3,4,5",
1543 "EventCode": "0x71",
1546 "UMask": "0x4",
1551 "Counter": "0,1,2,3,4,5",
1552 "EventCode": "0xc2",
1560 "Counter": "0,1,2,3",
1561 "EventCode": "0x76",
1564 "UMask": "0x1",
1568 "BriefDescription": "Uops executed on port 0",
1569 "Counter": "0,1,2,3,4,5,6,7",
1570 "EventCode": "0xb2",
1572 "PublicDescription": "Number of uops dispatch to execution port 0.",
1574 "UMask": "0x1",
1579 "Counter": "0,1,2,3,4,5,6,7",
1580 "EventCode": "0xb2",
1584 "UMask": "0x2",
1589 "Counter": "0,1,2,3,4,5,6,7",
1590 "EventCode": "0xb2",
1594 "UMask": "0x4",
1599 "Counter": "0,1,2,3,4,5,6,7",
1600 "EventCode": "0xb2",
1604 "UMask": "0x10",
1608 "BriefDescription": "Uops executed on ports 5 and 11",
1609 "Counter": "0,1,2,3,4,5,6,7",
1610 "EventCode": "0xb2",
1612 "PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
1614 "UMask": "0x20",
1619 "Counter": "0,1,2,3,4,5,6,7",
1620 "EventCode": "0xb2",
1624 "UMask": "0x40",
1629 "Counter": "0,1,2,3,4,5,6,7",
1630 "EventCode": "0xb2",
1634 "UMask": "0x80",
1638 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1639 "Counter": "0,1,2,3,4,5,6,7",
1641 "EventCode": "0xb1",
1643 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1645 "UMask": "0x2",
1649 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1650 "Counter": "0,1,2,3,4,5,6,7",
1652 "EventCode": "0xb1",
1654 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1656 "UMask": "0x2",
1660 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1661 "Counter": "0,1,2,3,4,5,6,7",
1663 "EventCode": "0xb1",
1665 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1667 "UMask": "0x2",
1671 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1672 "Counter": "0,1,2,3,4,5,6,7",
1674 "EventCode": "0xb1",
1676 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1678 "UMask": "0x2",
1682 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1683 "Counter": "0,1,2,3,4,5,6,7",
1685 "EventCode": "0xb1",
1687 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1689 "UMask": "0x1",
1693 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1694 "Counter": "0,1,2,3,4,5,6,7",
1696 "EventCode": "0xb1",
1698 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1700 "UMask": "0x1",
1704 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1705 "Counter": "0,1,2,3,4,5,6,7",
1707 "EventCode": "0xb1",
1709 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1711 "UMask": "0x1",
1715 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1716 "Counter": "0,1,2,3,4,5,6,7",
1718 "EventCode": "0xb1",
1720 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1722 "UMask": "0x1",
1727 "Counter": "0,1,2,3,4,5,6,7",
1729 "EventCode": "0xb1",
1734 "UMask": "0x1",
1739 "Counter": "0,1,2,3,4,5,6,7",
1742 "EventCode": "0xb1",
1746 "UMask": "0x1",
1750 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1751 "Counter": "0,1,2,3,4,5,6,7",
1752 "EventCode": "0xb1",
1755 "UMask": "0x1",
1760 "Counter": "0,1,2,3,4,5,6,7",
1761 "EventCode": "0xb1",
1765 "UMask": "0x10",
1770 "Counter": "0,1,2,3,4,5",
1771 "EventCode": "0x0e",
1773 …he number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops a…
1779 "Counter": "0,1,2,3,4,5,6,7",
1780 "EventCode": "0xae",
1784 "UMask": "0x1",
1789 "Counter": "0,1,2,3,4,5,6,7",
1791 "EventCode": "0xae",
1794 "UMask": "0x1",
1799 "Counter": "0,1,2,3,4,5",
1800 "EventCode": "0xc2",
1808 "Counter": "0,1,2,3,4,5,6,7",
1810 "EventCode": "0xc2",
1814 "UMask": "0x2",
1819 "Counter": "0,1,2,3,4,5,6,7",
1820 "EventCode": "0xc2",
1822 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1824 "UMask": "0x1",
1829 "Counter": "0,1,2,3,4,5",
1830 "EventCode": "0xc2",
1834 "UMask": "0x10",
1838 …tion": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
1839 "Counter": "0,1,2,3,4,5",
1840 "EventCode": "0xc2",
1845 "UMask": "0x1",
1850 "Counter": "0,1,2,3,4,5,6,7",
1851 "EventCode": "0xc2",
1853 "MSRIndex": "0x3F7",
1854 "MSRValue": "0x8",
1856 "UMask": "0x4",
1861 "Counter": "0,1,2,3,4,5,6,7",
1862 "EventCode": "0xc2",
1866 "UMask": "0x2",
1871 "Counter": "0,1,2,3,4,5,6,7",
1873 "EventCode": "0xc2",
1878 "UMask": "0x2",
1883 "Counter": "0,1,2,3,4,5,6,7",
1886 "EventCode": "0xc2",
1890 "UMask": "0x2",
1895 "Counter": "0,1,2,3,4,5",
1896 "EventCode": "0xc2",
1900 "UMask": "0x2",