Lines Matching full:was
40 "BriefDescription": "The instruction was flushed after becoming next-to-complete (NTC)."
45 …"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling…
50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
80 …-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR …
85 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
90 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the s…
95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t…
115 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
135 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not…
150 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the L…
160 …"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT…
165 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
170 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
175 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
195 …"BriefDescription": "At least one VSU instruction was issued to one of the VSU pipes. Up to 4 per …
205 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the V…
210 …"BriefDescription": "Cycles when dispatch was stalled for this thread due to an instruction cache …
215 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for…
220 …"BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held…
225 …h the next-to-complete (NTC) instruction is held at dispatch because the XVFC mapper/SRB was full."
230 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIE instructio…
235 … "Cycles in which the oldest instruction in the pipeline was executing in any unit before it was f…
260 …"BriefDescription": "Cycles dispatch is held because the STF mapper/SRB was full. Includes GPR (co…
265 …iefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruct…
270 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting to finish …
275 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instructio…
295 …which the oldest instruction in the pipeline was a store whose cache line was not resident in the …
300 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the no…
305 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed poi…
310 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
315 …Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was …
330 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
335 …n in the pipeline was finishing a load after its data was reloaded from a data source beyond the l…
340 …"BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an i…
345 …t-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR …
350 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
365 "BriefDescription": "Cycles dispatch is held because the XVFC mapper/SRB was full."
375 "BriefDescription": "A fixed point instruction was issued to the VSU."
385 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sourc…
395 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
400 … the oldest instruction in the pipeline cannot complete because the thread was blocked for any rea…
405 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
415 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction…
420 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruct…
425 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the B…
430 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting f…
435 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instructi…
440 …"BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch…
445 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any s…
450 …ruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU b…
460 "BriefDescription": "VSU instruction was issued to VSU pipe 3."
480 …"BriefDescription": "Cycles dispatch is held because the mapper/SRB was full. Includes GPR (count,…
500 …was held in a hottemp condition by the NCU Master. Multiply this count by 1000 to obtain the total…
505 …"BriefDescription": "Cycles when a TLBIE/SLBIEG/SLBIAG that targets this thread's LPAR was in flig…