Lines Matching +full:0 +full:x20
8 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE = 0x0,
9 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1,
10 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE = 0x2,
14 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT = 0,
26 u8 virtio_q_type[0x8];
27 u8 reserved_at_8[0x5];
28 u8 event_mode[0x3];
29 u8 queue_index[0x10];
31 u8 full_emulation[0x1];
32 u8 virtio_version_1_0[0x1];
33 u8 reserved_at_22[0x2];
34 u8 offload_type[0x4];
35 u8 event_qpn_or_msix[0x18];
37 u8 doorbell_stride_index[0x10];
38 u8 queue_size[0x10];
40 u8 device_emulation_id[0x20];
42 u8 desc_addr[0x40];
44 u8 used_addr[0x40];
46 u8 available_addr[0x40];
48 u8 virtio_q_mkey[0x20];
50 u8 max_tunnel_desc[0x10];
51 u8 reserved_at_170[0x8];
52 u8 error_type[0x8];
54 u8 umem_1_id[0x20];
56 u8 umem_1_size[0x20];
58 u8 umem_1_offset[0x40];
60 u8 umem_2_id[0x20];
62 u8 umem_2_size[0x20];
64 u8 umem_2_offset[0x40];
66 u8 umem_3_id[0x20];
68 u8 umem_3_size[0x20];
70 u8 umem_3_offset[0x40];
72 u8 counter_set_id[0x20];
74 u8 reserved_at_320[0x8];
75 u8 pd[0x18];
77 u8 reserved_at_340[0x20];
79 u8 desc_group_mkey[0x20];
81 u8 reserved_at_380[0x80];
85 u8 modify_field_select[0x40];
87 u8 reserved_at_40[0x20];
89 u8 vhca_id[0x10];
90 u8 reserved_at_70[0x10];
92 u8 queue_feature_bit_mask_12_3[0xa];
93 u8 dirty_bitmap_dump_enable[0x1];
94 u8 vhost_log_page[0x5];
95 u8 reserved_at_90[0xc];
96 u8 state[0x4];
98 u8 reserved_at_a0[0x5];
99 u8 queue_feature_bit_mask_2_0[0x3];
100 u8 tisn_or_qpn[0x18];
102 u8 dirty_bitmap_mkey[0x20];
104 u8 dirty_bitmap_size[0x20];
106 u8 dirty_bitmap_addr[0x40];
108 u8 hw_available_index[0x10];
109 u8 hw_used_index[0x10];
111 u8 reserved_at_160[0xa0];
145 MLX5_VIRTQ_MODIFY_MASK_STATE = (u64)1 << 0,
158 MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT = 0x0,
159 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY = 0x1,
160 MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND = 0x2,
161 MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR = 0x3,
169 MLX5_VIRTIO_NET_Q_OBJECT_NONE = 0xffffffff
173 MLX5_RQTC_LIST_Q_TYPE_RQ = 0x0,
174 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1,
188 u8 modify_field_select[0x40];
189 u8 reserved_at_40[0x40];
190 u8 received_desc[0x40];
191 u8 completed_desc[0x40];
192 u8 error_cqes[0x20];
193 u8 bad_desc_errors[0x20];
194 u8 exceed_max_chain[0x20];
195 u8 invalid_buffer[0x20];
196 u8 reserved_at_180[0x280];