28 #define AUXADC_CON1_SET_V	0x008
29 #define AUXADC_CON1_CLR_V	0x00c
30 #define AUXADC_CON2_V		0x010
31 #define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
33 #define APMIXED_SYS_TS_CON0	0x600
34 #define APMIXED_SYS_TS_CON1	0x604
37 #define TEMP_MONCTL0		0x000
38 #define TEMP_MONCTL1		0x004
39 #define TEMP_MONCTL2		0x008
40 #define TEMP_MONIDET0		0x014
41 #define TEMP_MONIDET1		0x018
42 #define TEMP_MSRCTL0		0x038
43 #define TEMP_MSRCTL1		0x03c
44 #define TEMP_AHBPOLL		0x040
45 #define TEMP_AHBTO		0x044
46 #define TEMP_ADCPNP0		0x048
47 #define TEMP_ADCPNP1		0x04c
48 #define TEMP_ADCPNP2		0x050
49 #define TEMP_ADCPNP3		0x0b4
51 #define TEMP_ADCMUX		0x054
52 #define TEMP_ADCEN		0x060
53 #define TEMP_PNPMUXADDR		0x064
54 #define TEMP_ADCMUXADDR		0x068
55 #define TEMP_ADCENADDR		0x074
56 #define TEMP_ADCVALIDADDR	0x078
57 #define TEMP_ADCVOLTADDR	0x07c
58 #define TEMP_RDCTRL		0x080
59 #define TEMP_ADCVALIDMASK	0x084
60 #define TEMP_ADCVOLTAGESHIFT	0x088
61 #define TEMP_ADCWRITECTRL	0x08c
62 #define TEMP_MSR0		0x090
63 #define TEMP_MSR1		0x094
64 #define TEMP_MSR2		0x098
65 #define TEMP_MSR3		0x0B8
67 #define TEMP_SPARE0		0x0f0
69 #define TEMP_ADCPNP0_1          0x148
70 #define TEMP_ADCPNP1_1          0x14c
71 #define TEMP_ADCPNP2_1          0x150
72 #define TEMP_MSR0_1             0x190
73 #define TEMP_MSR1_1             0x194
74 #define TEMP_MSR2_1             0x198
75 #define TEMP_ADCPNP3_1          0x1b4
76 #define TEMP_MSR3_1             0x1B8
78 #define PTPCORESEL		0x400
80 #define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
82 #define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
83 #define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
87 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
94 #define MT8173_TS1	0
130 #define CALIB_BUF0_VALID_V1		BIT(0)
131 #define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
132 #define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
133 #define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
134 #define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
135 #define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
136 #define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
137 #define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
138 #define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
139 #define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
140 #define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
141 #define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
147 #define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
148 #define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
149 #define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
150 #define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
151 #define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
152 #define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
153 #define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
154 #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
155 #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
161 #define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
162 #define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
163 #define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
164 #define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
165 #define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
166 #define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
167 #define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
168 #define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
169 #define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
188 #define MT2701_TS1	0
208 #define MT2712_TS1	0
232 #define MT7622_TS1	0
242 #define MT8183_TS1	0
280 #define MT7986_TS1			0
295 #define MT8365_TS1 0
367 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
368 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
390 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
391 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
410 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
411 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
430 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
431 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
441 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
443 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
449 static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
451 static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
466 static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
467 static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
496 			.sensors = mt8173_bank_data[0],
576 	.apmixed_buffer_ctl_set = 0,
635 	.apmixed_buffer_ctl_set = BIT(0),
695 	.apmixed_buffer_ctl_set = BIT(0),
716 	raw &= 0xfff;  in raw_to_mcelsius_v1()
736 	if (raw == 0)  in raw_to_mcelsius_v2()
737 		return 0;  in raw_to_mcelsius_v2()
739 	raw &= 0xfff;  in raw_to_mcelsius_v2()
749 	if (mt->o_slope_sign == 0)  in raw_to_mcelsius_v2()
761 	if (raw == 0)  in raw_to_mcelsius_v3()
762 		return 0;  in raw_to_mcelsius_v3()
764 	raw &= 0xfff;  in raw_to_mcelsius_v3()
789 		val &= ~0xf;  in mtk_thermal_get_bank()
823 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {  in mtk_thermal_bank_temperature()
854 	for (i = 0; i < mt->conf->num_banks; i++) {  in mtk_read_temp()
866 	return 0;  in mtk_read_temp()
905 	writel(0x0, controller_base + TEMP_MSRCTL0);  in mtk_thermal_init_bank()
908 	writel(0xffffffff, controller_base + TEMP_AHBTO);  in mtk_thermal_init_bank()
911 	writel(0x0, controller_base + TEMP_MONIDET0);  in mtk_thermal_init_bank()
912 	writel(0x0, controller_base + TEMP_MONIDET1);  in mtk_thermal_init_bank()
942 	/* AHB address for auxadc enable (channel 0 immediate mode selected) */  in mtk_thermal_init_bank()
955 	writel(0x0, controller_base + TEMP_RDCTRL);  in mtk_thermal_init_bank()
962 	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);  in mtk_thermal_init_bank()
968 	for (i = 0; i < conf->bank_data[num].num_sensors; i++)  in mtk_thermal_init_bank()
986 	if (of_address_to_resource(np, 0, &res))  in of_get_phys_base()
996 	if (!(buf[0] & CALIB_BUF0_VALID_V1))  in mtk_thermal_extract_efuse_v1()
1001 	for (i = 0; i < mt->conf->num_sensors; i++) {  in mtk_thermal_extract_efuse_v1()
1004 			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1007 			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1027 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1029 	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))  in mtk_thermal_extract_efuse_v1()
1030 		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1032 		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);  in mtk_thermal_extract_efuse_v1()
1034 	return 0;  in mtk_thermal_extract_efuse_v1()
1042 	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1043 	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1044 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1045 	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);  in mtk_thermal_extract_efuse_v2()
1051 	return 0;  in mtk_thermal_extract_efuse_v2()
1059 	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);  in mtk_thermal_extract_efuse_v3()
1060 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);  in mtk_thermal_extract_efuse_v3()
1061 	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);  in mtk_thermal_extract_efuse_v3()
1067 	if (CALIB_BUF1_ID_V3(buf[1]) == 0)  in mtk_thermal_extract_efuse_v3()
1068 		mt->o_slope = 0;  in mtk_thermal_extract_efuse_v3()
1070 	return 0;  in mtk_thermal_extract_efuse_v3()
1079 	int i, ret = 0;  in mtk_thermal_get_calibration_data()
1084 	for (i = 0; i < mt->conf->num_sensors; i++)  in mtk_thermal_get_calibration_data()
1087 	mt->o_slope = 0;  in mtk_thermal_get_calibration_data()
1093 		return 0;  in mtk_thermal_get_calibration_data()
1126 		ret = 0;  in mtk_thermal_get_calibration_data()
1188 	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);  in mtk_thermal_release_periodic_ts()
1189 	writel(0x1, mt->thermal_base + TEMP_MONCTL0);  in mtk_thermal_release_periodic_ts()
1191 	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);  in mtk_thermal_release_periodic_ts()
1209 	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);  in mtk_thermal_probe()
1221 	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);  in mtk_thermal_probe()
1227 	auxadc_base = of_iomap(auxadc, 0);  in mtk_thermal_probe()
1237 	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);  in mtk_thermal_probe()
1243 	apmixed_base = of_iomap(apmixedsys, 0);  in mtk_thermal_probe()
1283 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)  in mtk_thermal_probe()
1284 		for (i = 0; i < mt->conf->num_banks; i++)  in mtk_thermal_probe()
1288 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,  in mtk_thermal_probe()
1297 	return 0;  in mtk_thermal_probe()