Lines Matching defs:x
50 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
52 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
56 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument
58 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument
62 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ argument
64 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\ argument
73 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ argument
75 #define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\ argument
79 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\ argument
81 #define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\ argument
85 #define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\ argument
87 #define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\ argument
91 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\ argument
93 #define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\ argument
97 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\ argument
99 #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\ argument
108 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\ argument
110 #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\ argument
119 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\ argument
121 #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\ argument
130 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\ argument
132 #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\ argument
136 #define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\ argument
138 #define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\ argument
142 #define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\ argument
144 #define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\ argument
148 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\ argument
150 #define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\ argument
154 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\ argument
156 #define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\ argument
160 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\ argument
162 #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\ argument
171 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\ argument
173 #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\ argument
177 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\ argument
179 #define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\ argument
183 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\ argument
185 #define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\ argument
189 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\ argument
191 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\ argument
195 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\ argument
197 #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\ argument
206 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\ argument
208 #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\ argument
212 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\ argument
214 #define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\ argument
218 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\ argument
220 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\ argument
224 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\ argument
226 #define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\ argument
230 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\ argument
232 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\ argument
236 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\ argument
238 #define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\ argument
242 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\ argument
244 #define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\ argument
248 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\ argument
250 #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\ argument
259 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\ argument
261 #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\ argument
265 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\ argument
267 #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\ argument
276 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\ argument
278 #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\ argument
282 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\ argument
284 #define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\ argument
288 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\ argument
290 #define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\ argument
294 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\ argument
296 #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\ argument
305 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\ argument
307 #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\ argument
316 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\ argument
318 #define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\ argument
322 #define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\ argument
324 #define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\ argument
328 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\ argument
330 #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\ argument
339 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\ argument
341 #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\ argument
350 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\ argument
352 #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\ argument
361 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\ argument
363 #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\ argument
372 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\ argument
374 #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\ argument
378 #define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\ argument
380 #define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\ argument
384 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\ argument
386 #define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\ argument
390 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\ argument
392 #define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\ argument
396 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\ argument
398 #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\ argument
407 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\ argument
409 #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\ argument
418 #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\ argument
420 #define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\ argument
424 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\ argument
426 #define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\ argument
430 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\ argument
432 #define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\ argument
436 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\ argument
438 #define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\ argument
442 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\ argument
444 #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\ argument
453 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\ argument
455 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\ argument
459 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\ argument
461 #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\ argument
470 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\ argument
472 #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\ argument
481 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\ argument
483 #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\ argument
487 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\ argument
489 #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\ argument
498 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\ argument
500 #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\ argument
504 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\ argument
506 #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\ argument
515 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\ argument
517 #define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\ argument
521 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\ argument
523 #define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\ argument
527 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\ argument
529 #define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\ argument
533 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\ argument
535 #define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\ argument
539 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\ argument
541 #define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\ argument
545 #define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\ argument
547 #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\ argument
556 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\ argument
558 #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\ argument
562 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\ argument
564 #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\ argument
573 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ argument
575 #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ argument
579 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\ argument
581 #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\ argument
590 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\ argument
592 #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\ argument
596 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\ argument
598 #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\ argument
607 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\ argument
609 #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\ argument
613 #define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\ argument
615 #define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\ argument
619 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\ argument
621 #define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\ argument
625 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\ argument
627 #define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\ argument
631 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\ argument
633 #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\ argument
642 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\ argument
644 #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\ argument
648 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\ argument
650 #define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\ argument
654 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\ argument
656 #define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\ argument
660 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\ argument
662 #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\ argument
671 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\ argument
673 #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\ argument
677 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\ argument
679 #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\ argument
688 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\ argument
690 #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\ argument
694 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\ argument
696 #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\ argument
705 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\ argument
707 #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\ argument
711 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\ argument
713 #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\ argument
722 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\ argument
724 #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\ argument
733 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\ argument
735 #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\ argument
744 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\ argument
746 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\ argument
750 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\ argument
752 #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\ argument
761 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\ argument
763 #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\ argument
767 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\ argument
769 #define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\ argument
773 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\ argument
775 #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\ argument
784 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\ argument
786 #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\ argument
790 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\ argument
792 #define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\ argument
796 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\ argument
798 #define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\ argument
802 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\ argument
804 #define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\ argument
808 #define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\ argument
810 #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\ argument
819 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\ argument
821 #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\ argument
830 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\ argument
832 #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\ argument
836 #define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\ argument
838 #define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\ argument
842 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\ argument
844 #define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\ argument
848 #define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\ argument
850 #define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\ argument
854 #define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\ argument
856 #define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\ argument
860 #define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\ argument
862 #define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\ argument
866 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\ argument
868 #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\ argument
877 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\ argument
879 #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\ argument
883 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
885 #define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
889 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\ argument
891 #define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\ argument
895 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\ argument
897 #define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\ argument
901 #define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\ argument
903 #define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\ argument
907 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\ argument
909 #define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\ argument
913 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\ argument
915 #define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\ argument
919 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\ argument
921 #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\ argument
930 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\ argument
932 #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\ argument
936 #define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\ argument
938 #define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\ argument
942 #define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\ argument
944 #define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\ argument
948 #define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\ argument
950 #define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\ argument
954 #define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\ argument
956 #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\ argument
965 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\ argument
967 #define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\ argument
971 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\ argument
973 #define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\ argument
977 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\ argument
979 #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\ argument
988 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\ argument
990 #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\ argument
994 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\ argument
996 #define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\ argument
1000 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\ argument
1002 #define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\ argument
1006 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\ argument
1008 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\ argument
1012 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\ argument
1014 #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\ argument
1023 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\ argument
1025 #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\ argument
1034 #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\ argument
1036 #define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\ argument
1040 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument
1042 #define SD10G_LANE_LANE_DF_LOL_GET(x)\ argument
1046 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
1048 #define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
1052 #define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\ argument
1054 #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\ argument
1063 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\ argument
1065 #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\ argument
1069 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\ argument
1071 #define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\ argument
1075 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\ argument
1077 #define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\ argument
1081 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\ argument
1083 #define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\ argument
1087 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\ argument
1089 #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\ argument
1098 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\ argument
1100 #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\ argument
1104 #define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\ argument
1106 #define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\ argument
1110 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\ argument
1112 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\ argument
1116 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\ argument
1118 #define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\ argument
1122 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\ argument
1124 #define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\ argument
1128 #define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\ argument
1130 #define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\ argument
1134 #define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\ argument
1136 #define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\ argument
1140 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\ argument
1142 #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\ argument
1151 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\ argument
1153 #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\ argument
1157 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\ argument
1159 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\ argument
1163 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\ argument
1165 #define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\ argument
1169 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\ argument
1171 #define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\ argument
1175 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\ argument
1177 #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\ argument
1186 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\ argument
1188 #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\ argument
1192 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\ argument
1194 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\ argument
1198 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\ argument
1200 #define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\ argument
1204 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\ argument
1206 #define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\ argument
1210 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\ argument
1212 #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\ argument
1221 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\ argument
1223 #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\ argument
1227 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\ argument
1229 #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\ argument
1238 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\ argument
1240 #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\ argument
1244 #define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\ argument
1246 #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\ argument
1255 #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\ argument
1257 #define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\ argument
1261 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\ argument
1263 #define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\ argument
1267 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\ argument
1269 #define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\ argument
1273 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\ argument
1275 #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\ argument
1284 #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\ argument
1286 #define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\ argument
1290 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\ argument
1292 #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\ argument
1301 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\ argument
1303 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\ argument
1307 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
1309 #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
1313 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\ argument
1315 #define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\ argument
1319 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\ argument
1321 #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\ argument
1330 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\ argument
1332 #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\ argument
1336 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\ argument
1338 #define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\ argument
1342 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\ argument
1344 #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\ argument
1353 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\ argument
1355 #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\ argument
1359 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\ argument
1361 #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\ argument
1370 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\ argument
1372 #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\ argument
1381 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\ argument
1383 #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\ argument
1387 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\ argument
1389 #define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\ argument
1393 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\ argument
1395 #define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\ argument
1399 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\ argument
1401 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\ argument
1405 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\ argument
1407 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\ argument
1411 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\ argument
1413 #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\ argument
1422 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\ argument
1424 #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\ argument
1433 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\ argument
1435 #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\ argument
1444 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\ argument
1446 #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\ argument
1450 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\ argument
1452 #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\ argument
1461 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\ argument
1463 #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\ argument
1472 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\ argument
1474 #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\ argument
1478 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\ argument
1480 #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\ argument
1489 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ argument
1491 #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\ argument
1495 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\ argument
1497 #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\ argument
1506 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\ argument
1508 #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\ argument
1517 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\ argument
1519 #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\ argument
1523 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\ argument
1525 #define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\ argument
1529 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\ argument
1531 #define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\ argument
1535 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\ argument
1537 #define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\ argument
1541 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\ argument
1543 #define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\ argument
1547 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\ argument
1549 #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\ argument
1558 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\ argument
1560 #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\ argument
1564 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\ argument
1566 #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\ argument
1575 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\ argument
1577 #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\ argument
1581 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\ argument
1583 #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\ argument
1592 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\ argument
1594 #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\ argument
1598 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\ argument
1600 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\ argument
1604 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\ argument
1606 #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\ argument
1615 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\ argument
1617 #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\ argument
1626 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\ argument
1628 #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\ argument
1637 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\ argument
1639 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\ argument
1643 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\ argument
1645 #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\ argument
1649 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\ argument
1651 #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\ argument
1660 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
1662 #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
1666 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\ argument
1668 #define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\ argument
1672 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\ argument
1674 #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\ argument
1683 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\ argument
1685 #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\ argument
1689 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\ argument
1691 #define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\ argument
1695 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\ argument
1697 #define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\ argument
1701 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\ argument
1703 #define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\ argument
1707 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\ argument
1709 #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\ argument
1718 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\ argument
1720 #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\ argument
1724 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\ argument
1726 #define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\ argument
1730 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\ argument
1732 #define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\ argument
1736 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\ argument
1738 #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\ argument
1747 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\ argument
1749 #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\ argument
1758 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\ argument
1760 #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\ argument
1764 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\ argument
1766 #define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\ argument
1770 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\ argument
1772 #define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\ argument
1776 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\ argument
1778 #define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\ argument
1782 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\ argument
1784 #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\ argument
1793 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\ argument
1795 #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\ argument
1799 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\ argument
1801 #define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\ argument
1805 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\ argument
1807 #define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\ argument
1811 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\ argument
1813 #define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\ argument
1817 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\ argument
1819 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\ argument
1823 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\ argument
1825 #define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\ argument
1829 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\ argument
1831 #define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\ argument
1835 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\ argument
1837 #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\ argument
1846 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\ argument
1848 #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\ argument
1852 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\ argument
1854 #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\ argument
1863 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\ argument
1865 #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\ argument
1874 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\ argument
1876 #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\ argument
1880 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\ argument
1882 #define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\ argument
1886 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\ argument
1888 #define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\ argument
1892 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\ argument
1894 #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\ argument
1903 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\ argument
1905 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\ argument
1909 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\ argument
1911 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\ argument
1915 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\ argument
1917 #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\ argument
1921 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\ argument
1923 #define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\ argument
1927 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\ argument
1929 #define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\ argument
1933 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\ argument
1935 #define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\ argument
1939 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\ argument
1941 #define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\ argument
1945 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\ argument
1947 #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\ argument
1956 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\ argument
1958 #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\ argument
1962 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\ argument
1964 #define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\ argument
1968 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\ argument
1970 #define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\ argument
1974 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\ argument
1976 #define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\ argument
1980 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\ argument
1982 #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\ argument
1991 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\ argument
1993 #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\ argument
2002 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\ argument
2004 #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\ argument
2013 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\ argument
2015 #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\ argument
2024 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\ argument
2026 #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\ argument
2035 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\ argument
2037 #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\ argument
2041 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\ argument
2043 #define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\ argument
2047 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\ argument
2049 #define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\ argument
2053 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\ argument
2055 #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\ argument
2064 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\ argument
2066 #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\ argument
2070 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\ argument
2072 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\ argument
2076 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\ argument
2078 #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\ argument
2087 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\ argument
2089 #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\ argument
2093 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\ argument
2095 #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\ argument
2104 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\ argument
2106 #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\ argument
2110 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\ argument
2112 #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\ argument
2121 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\ argument
2123 #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\ argument
2127 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\ argument
2129 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\ argument
2133 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\ argument
2135 #define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\ argument
2139 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\ argument
2141 #define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\ argument
2145 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\ argument
2147 #define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\ argument
2151 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\ argument
2153 #define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\ argument
2157 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\ argument
2159 #define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\ argument
2163 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\ argument
2165 #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\ argument
2174 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\ argument
2176 #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\ argument
2180 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\ argument
2182 #define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\ argument
2186 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\ argument
2188 #define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\ argument
2192 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\ argument
2194 #define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\ argument
2198 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\ argument
2200 #define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\ argument
2204 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\ argument
2206 #define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\ argument
2210 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\ argument
2212 #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\ argument
2221 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\ argument
2223 #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\ argument
2232 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\ argument
2234 #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\ argument
2243 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\ argument
2245 #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\ argument
2254 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\ argument
2256 #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\ argument
2265 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\ argument
2267 #define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\ argument
2271 #define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\ argument
2273 #define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\ argument
2277 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
2279 #define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
2283 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\ argument
2285 #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\ argument
2294 #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\ argument
2296 #define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\ argument
2300 #define SD6G_LANE_LANE_DF_LOL_SET(x)\ argument
2302 #define SD6G_LANE_LANE_DF_LOL_GET(x)\ argument
2306 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\ argument
2308 #define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\ argument
2312 #define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\ argument
2314 #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\ argument
2322 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\ argument
2324 #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\ argument
2328 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\ argument
2330 #define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\ argument
2334 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\ argument
2336 #define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\ argument
2340 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\ argument
2342 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\ argument
2350 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\ argument
2352 #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\ argument
2356 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\ argument
2358 #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ argument
2366 #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\ argument
2368 #define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\ argument
2372 #define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\ argument
2374 #define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\ argument
2378 #define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\ argument
2380 #define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\ argument
2384 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\ argument
2386 #define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\ argument
2390 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\ argument
2392 #define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\ argument
2396 #define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\ argument
2398 #define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\ argument
2402 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\ argument
2404 #define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\ argument
2408 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\ argument
2410 #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\ argument
2418 #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\ argument
2420 #define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\ argument
2424 #define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\ argument
2426 #define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\ argument
2430 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\ argument
2432 #define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\ argument
2436 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\ argument
2438 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\ argument
2442 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\ argument
2444 #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\ argument
2452 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\ argument
2454 #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\ argument
2458 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\ argument
2460 #define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\ argument
2464 #define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\ argument
2466 #define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\ argument
2470 #define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\ argument
2472 #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\ argument
2480 #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\ argument
2482 #define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\ argument
2486 #define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\ argument
2488 #define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\ argument
2492 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\ argument
2494 #define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\ argument
2498 #define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\ argument
2500 #define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\ argument
2504 #define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\ argument
2506 #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\ argument
2514 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\ argument
2516 #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\ argument
2524 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\ argument
2526 #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\ argument
2530 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\ argument
2532 #define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\ argument
2536 #define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\ argument
2538 #define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\ argument
2542 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\ argument
2544 #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\ argument
2552 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\ argument
2554 #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\ argument
2562 #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\ argument
2564 #define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\ argument
2568 #define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\ argument
2570 #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\ argument
2578 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\ argument
2580 #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\ argument
2584 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\ argument
2586 #define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\ argument
2590 #define SD_CMU_CMU_45_RESERVED_SET(x)\ argument
2592 #define SD_CMU_CMU_45_RESERVED_GET(x)\ argument
2596 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\ argument
2598 #define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\ argument
2602 #define SD_CMU_CMU_45_RESERVED_2_SET(x)\ argument
2604 #define SD_CMU_CMU_45_RESERVED_2_GET(x)\ argument
2608 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\ argument
2610 #define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\ argument
2614 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\ argument
2616 #define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\ argument
2620 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\ argument
2622 #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\ argument
2630 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\ argument
2632 #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\ argument
2640 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\ argument
2642 #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\ argument
2646 #define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\ argument
2648 #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\ argument
2657 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\ argument
2659 #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\ argument
2663 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\ argument
2665 #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\ argument
2673 #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\ argument
2675 #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\ argument
2683 #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\ argument
2685 #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\ argument
2693 #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\ argument
2695 #define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\ argument
2699 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ argument
2701 #define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ argument
2705 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\ argument
2707 #define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\ argument
2711 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\ argument
2713 #define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\ argument
2717 #define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\ argument
2719 #define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\ argument
2723 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\ argument
2725 #define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\ argument
2729 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\ argument
2731 #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\ argument
2739 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ argument
2741 #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ argument
2745 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\ argument
2747 #define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\ argument
2751 #define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\ argument
2753 #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ argument
2761 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\ argument
2763 #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\ argument
2771 #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\ argument
2773 #define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\ argument
2777 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument
2779 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument
2783 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument
2785 #define SD_LANE_MISC_MUX_ENA_GET(x)\ argument
2790 #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\ argument
2792 #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\ argument
2800 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\ argument
2802 #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\ argument
2806 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\ argument
2808 #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\ argument
2817 #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\ argument
2819 #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\ argument
2828 #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\ argument
2830 #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\ argument
2839 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\ argument
2841 #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\ argument
2845 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\ argument
2847 #define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\ argument
2851 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\ argument
2853 #define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\ argument
2857 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\ argument
2859 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\ argument
2863 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\ argument
2865 #define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\ argument
2869 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\ argument
2871 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\ argument
2875 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\ argument
2877 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\ argument
2881 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\ argument
2883 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\ argument
2887 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\ argument
2889 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\ argument
2893 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\ argument
2895 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\ argument
2899 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\ argument
2901 #define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\ argument
2905 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\ argument
2907 #define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\ argument
2911 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\ argument
2913 #define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\ argument
2917 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\ argument
2919 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\ argument
2923 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\ argument
2925 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\ argument
2929 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\ argument
2931 #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\ argument
2940 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\ argument
2942 #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\ argument
2946 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\ argument
2948 #define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\ argument
2952 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\ argument
2954 #define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\ argument
2958 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\ argument
2960 #define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\ argument
2964 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\ argument
2966 #define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\ argument
2970 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\ argument
2972 #define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\ argument
2976 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\ argument
2978 #define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\ argument
2982 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\ argument
2984 #define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\ argument
2988 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\ argument
2990 #define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\ argument
2994 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\ argument
2996 #define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\ argument
3000 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\ argument
3002 #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\ argument
3011 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ argument
3013 #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\ argument
3017 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\ argument
3019 #define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\ argument
3023 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\ argument
3025 #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ argument
3034 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\ argument
3036 #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\ argument