Lines Matching +full:addr +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
10 #include <linux/crc-itu-t.h>
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
52 } gpios; member
119 u8 addr[3]; member
123 u8 addr[3]; member
128 u8 addr[3]; member
133 u8 addr[2]; member
138 u8 addr[3]; member
165 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_parse_gpios()
166 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_parse_gpios()
167 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_parse_gpios() local
170 gpios->enable = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
173 if (gpios->enable) { in wilc_parse_gpios()
175 gpios->reset = devm_gpiod_get(&spi->dev, in wilc_parse_gpios()
177 if (IS_ERR(gpios->reset)) { in wilc_parse_gpios()
178 dev_err(&spi->dev, "missing reset gpio.\n"); in wilc_parse_gpios()
179 return PTR_ERR(gpios->reset); in wilc_parse_gpios()
182 gpios->reset = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
190 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_wlan_power()
191 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_wlan_power() local
195 gpiod_set_value(gpios->enable, 1); in wilc_wlan_power()
198 gpiod_set_value(gpios->reset, 0); in wilc_wlan_power()
201 gpiod_set_value(gpios->reset, 1); in wilc_wlan_power()
203 gpiod_set_value(gpios->enable, 0); in wilc_wlan_power()
216 return -ENOMEM; in wilc_bus_probe()
218 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); in wilc_bus_probe()
223 wilc->dev = &spi->dev; in wilc_bus_probe()
224 wilc->bus_data = spi_priv; in wilc_bus_probe()
225 wilc->dev_irq_num = spi->irq; in wilc_bus_probe()
231 wilc->rtc_clk = devm_clk_get_optional_enabled(&spi->dev, "rtc"); in wilc_bus_probe()
232 if (IS_ERR(wilc->rtc_clk)) { in wilc_bus_probe()
233 ret = PTR_ERR(wilc->rtc_clk); in wilc_bus_probe()
237 dev_info(&spi->dev, "Selected CRC config: crc7=%s, crc16=%s\n", in wilc_bus_probe()
272 wiphy_unregister(wilc->wiphy); in wilc_bus_probe()
277 wiphy_free(wilc->wiphy); in wilc_bus_probe()
286 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_bus_remove()
289 wiphy_unregister(wilc->wiphy); in wilc_bus_remove()
290 wiphy_free(wilc->wiphy); in wilc_bus_remove()
321 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx()
337 return -ENOMEM; in wilc_spi_tx()
340 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); in wilc_spi_tx()
348 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx()
352 dev_err(&spi->dev, in wilc_spi_tx()
355 ret = -EINVAL; in wilc_spi_tx()
363 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_rx()
380 return -ENOMEM; in wilc_spi_rx()
390 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_rx()
393 dev_err(&spi->dev, in wilc_spi_rx()
396 ret = -EINVAL; in wilc_spi_rx()
404 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx_rx()
426 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx_rx()
428 dev_err(&spi->dev, in wilc_spi_tx_rx()
431 ret = -EINVAL; in wilc_spi_tx_rx()
439 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_write()
440 struct wilc_spi *spi_priv = wilc->bus_data; in spi_data_write()
469 dev_err(&spi->dev, in spi_data_write()
471 result = -EINVAL; in spi_data_write()
479 dev_err(&spi->dev, in spi_data_write()
481 result = -EINVAL; in spi_data_write()
488 if (spi_priv->crc16_enabled) { in spi_data_write()
493 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); in spi_data_write()
494 result = -EINVAL; in spi_data_write()
503 sz -= nbytes; in spi_data_write()
522 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_single_read()
523 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_single_read()
534 c->cmd_type = cmd; in wilc_spi_single_read()
536 c->u.simple_cmd.addr[0] = adr >> 16; in wilc_spi_single_read()
537 c->u.simple_cmd.addr[1] = adr >> 8; in wilc_spi_single_read()
538 c->u.simple_cmd.addr[2] = adr; in wilc_spi_single_read()
540 c->u.simple_cmd.addr[0] = adr >> 8; in wilc_spi_single_read()
542 c->u.simple_cmd.addr[0] |= BIT(7); in wilc_spi_single_read()
543 c->u.simple_cmd.addr[1] = adr; in wilc_spi_single_read()
544 c->u.simple_cmd.addr[2] = 0x0; in wilc_spi_single_read()
546 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); in wilc_spi_single_read()
547 return -EINVAL; in wilc_spi_single_read()
553 if (spi_priv->crc7_enabled) { in wilc_spi_single_read()
554 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_single_read()
560 dev_err(&spi->dev, in wilc_spi_single_read()
563 return -EINVAL; in wilc_spi_single_read()
567 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_single_read()
568 return -EINVAL; in wilc_spi_single_read()
572 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_single_read()
573 if (!spi_priv->probing_crc) in wilc_spi_single_read()
574 dev_err(&spi->dev, in wilc_spi_single_read()
576 cmd, r->rsp_cmd_type); in wilc_spi_single_read()
577 return -EINVAL; in wilc_spi_single_read()
580 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_single_read()
581 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_single_read()
582 r->status); in wilc_spi_single_read()
583 return -EINVAL; in wilc_spi_single_read()
587 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) in wilc_spi_single_read()
591 dev_err(&spi->dev, "Error, data start missing\n"); in wilc_spi_single_read()
592 return -EINVAL; in wilc_spi_single_read()
595 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; in wilc_spi_single_read()
598 memcpy(b, r_data->data, 4); in wilc_spi_single_read()
600 if (!clockless && spi_priv->crc16_enabled) { in wilc_spi_single_read()
601 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; in wilc_spi_single_read()
602 crc_calc = crc_itu_t(0xffff, r_data->data, 4); in wilc_spi_single_read()
604 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_single_read()
607 return -EINVAL; in wilc_spi_single_read()
617 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_cmd()
618 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_write_cmd()
627 c->cmd_type = cmd; in wilc_spi_write_cmd()
629 c->u.internal_w_cmd.addr[0] = adr >> 8; in wilc_spi_write_cmd()
631 c->u.internal_w_cmd.addr[0] |= BIT(7); in wilc_spi_write_cmd()
633 c->u.internal_w_cmd.addr[1] = adr; in wilc_spi_write_cmd()
634 c->u.internal_w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
636 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
637 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
639 c->u.w_cmd.addr[0] = adr >> 16; in wilc_spi_write_cmd()
640 c->u.w_cmd.addr[1] = adr >> 8; in wilc_spi_write_cmd()
641 c->u.w_cmd.addr[2] = adr; in wilc_spi_write_cmd()
642 c->u.w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
644 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
645 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
647 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); in wilc_spi_write_cmd()
648 return -EINVAL; in wilc_spi_write_cmd()
651 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
657 dev_err(&spi->dev, in wilc_spi_write_cmd()
660 return -EINVAL; in wilc_spi_write_cmd()
664 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_write_cmd()
665 return -EINVAL; in wilc_spi_write_cmd()
673 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_write_cmd()
674 dev_err(&spi->dev, in wilc_spi_write_cmd()
676 cmd, r->rsp_cmd_type); in wilc_spi_write_cmd()
677 return -EINVAL; in wilc_spi_write_cmd()
680 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_write_cmd()
681 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_write_cmd()
682 r->status); in wilc_spi_write_cmd()
683 return -EINVAL; in wilc_spi_write_cmd()
691 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_dma_rw()
692 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_dma_rw()
704 c->cmd_type = cmd; in wilc_spi_dma_rw()
706 c->u.dma_cmd.addr[0] = adr >> 16; in wilc_spi_dma_rw()
707 c->u.dma_cmd.addr[1] = adr >> 8; in wilc_spi_dma_rw()
708 c->u.dma_cmd.addr[2] = adr; in wilc_spi_dma_rw()
709 c->u.dma_cmd.size[0] = sz >> 8; in wilc_spi_dma_rw()
710 c->u.dma_cmd.size[1] = sz; in wilc_spi_dma_rw()
712 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
713 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
715 c->u.dma_cmd_ext.addr[0] = adr >> 16; in wilc_spi_dma_rw()
716 c->u.dma_cmd_ext.addr[1] = adr >> 8; in wilc_spi_dma_rw()
717 c->u.dma_cmd_ext.addr[2] = adr; in wilc_spi_dma_rw()
718 c->u.dma_cmd_ext.size[0] = sz >> 16; in wilc_spi_dma_rw()
719 c->u.dma_cmd_ext.size[1] = sz >> 8; in wilc_spi_dma_rw()
720 c->u.dma_cmd_ext.size[2] = sz; in wilc_spi_dma_rw()
722 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
723 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
725 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", in wilc_spi_dma_rw()
727 return -EINVAL; in wilc_spi_dma_rw()
729 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
735 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", in wilc_spi_dma_rw()
737 return -EINVAL; in wilc_spi_dma_rw()
741 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_dma_rw()
742 return -EINVAL; in wilc_spi_dma_rw()
746 if (r->rsp_cmd_type != cmd) { in wilc_spi_dma_rw()
747 dev_err(&spi->dev, in wilc_spi_dma_rw()
749 cmd, r->rsp_cmd_type); in wilc_spi_dma_rw()
750 return -EINVAL; in wilc_spi_dma_rw()
753 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_dma_rw()
754 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_dma_rw()
755 r->status); in wilc_spi_dma_rw()
756 return -EINVAL; in wilc_spi_dma_rw()
774 dev_err(&spi->dev, in wilc_spi_dma_rw()
776 return -EINVAL; in wilc_spi_dma_rw()
780 } while (retry--); in wilc_spi_dma_rw()
786 dev_err(&spi->dev, in wilc_spi_dma_rw()
788 return -EINVAL; in wilc_spi_dma_rw()
794 if (spi_priv->crc16_enabled) { in wilc_spi_dma_rw()
796 dev_err(&spi->dev, in wilc_spi_dma_rw()
798 return -EINVAL; in wilc_spi_dma_rw()
803 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_dma_rw()
806 return -EINVAL; in wilc_spi_dma_rw()
811 sz -= nbytes; in wilc_spi_dma_rw()
818 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_special_cmd()
819 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_special_cmd()
826 return -EINVAL; in wilc_spi_special_cmd()
831 c->cmd_type = cmd; in wilc_spi_special_cmd()
834 memset(c->u.simple_cmd.addr, 0xFF, 3); in wilc_spi_special_cmd()
839 if (spi_priv->crc7_enabled) { in wilc_spi_special_cmd()
840 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_special_cmd()
844 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", in wilc_spi_special_cmd()
846 return -EINVAL; in wilc_spi_special_cmd()
850 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_special_cmd()
851 return -EINVAL; in wilc_spi_special_cmd()
855 if (r->rsp_cmd_type != cmd) { in wilc_spi_special_cmd()
856 if (!spi_priv->probing_crc) in wilc_spi_special_cmd()
857 dev_err(&spi->dev, in wilc_spi_special_cmd()
859 cmd, r->rsp_cmd_type); in wilc_spi_special_cmd()
860 return -EINVAL; in wilc_spi_special_cmd()
863 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_special_cmd()
864 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_special_cmd()
865 r->status); in wilc_spi_special_cmd()
866 return -EINVAL; in wilc_spi_special_cmd()
871 static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr) in wilc_spi_reset_cmd_sequence() argument
873 struct spi_device *spi = to_spi_device(wl->dev); in wilc_spi_reset_cmd_sequence()
874 struct wilc_spi *spi_priv = wl->bus_data; in wilc_spi_reset_cmd_sequence()
876 if (!spi_priv->probing_crc) in wilc_spi_reset_cmd_sequence()
877 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr); in wilc_spi_reset_cmd_sequence()
884 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) in wilc_spi_read_reg() argument
886 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read_reg()
892 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { in wilc_spi_read_reg()
899 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); in wilc_spi_read_reg()
909 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); in wilc_spi_read_reg()
910 wilc_spi_reset_cmd_sequence(wilc, i, addr); in wilc_spi_read_reg()
916 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) in wilc_spi_read() argument
918 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read()
923 return -EINVAL; in wilc_spi_read()
926 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, in wilc_spi_read()
931 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); in wilc_spi_read()
933 wilc_spi_reset_cmd_sequence(wilc, i, addr); in wilc_spi_read()
941 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_write()
950 dev_err(&spi->dev, "Failed internal write cmd...\n"); in spi_internal_write()
960 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_read()
961 struct wilc_spi *spi_priv = wilc->bus_data; in spi_internal_read()
972 if (!spi_priv->probing_crc) in spi_internal_read()
973 dev_err(&spi->dev, "Failed internal read cmd...\n"); in spi_internal_read()
987 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) in wilc_spi_write_reg() argument
989 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_reg()
995 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { in wilc_spi_write_reg()
1002 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); in wilc_spi_write_reg()
1006 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); in wilc_spi_write_reg()
1011 wilc_spi_reset_cmd_sequence(wilc, i, addr); in wilc_spi_write_reg()
1018 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_rsp()
1028 * second-to-last packet before the one for the final packet. in spi_data_rsp()
1036 dev_err(&spi->dev, "Failed bus error...\n"); in spi_data_rsp()
1040 for (i = sizeof(rsp) - 2; i >= 0; --i) in spi_data_rsp()
1045 dev_err(&spi->dev, in spi_data_rsp()
1048 return -1; in spi_data_rsp()
1055 dev_err(&spi->dev, "Data response error (%02x %02x)\n", in spi_data_rsp()
1057 return -1; in spi_data_rsp()
1062 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) in wilc_spi_write() argument
1064 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write()
1072 return -EINVAL; in wilc_spi_write()
1075 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, in wilc_spi_write()
1078 dev_err(&spi->dev, in wilc_spi_write()
1079 "Failed cmd, write block (%08x)...\n", addr); in wilc_spi_write()
1080 wilc_spi_reset_cmd_sequence(wilc, i, addr); in wilc_spi_write()
1089 dev_err(&spi->dev, "Failed block data write...\n"); in wilc_spi_write()
1090 wilc_spi_reset_cmd_sequence(wilc, i, addr); in wilc_spi_write()
1099 dev_err(&spi->dev, "Failed block data rsp...\n"); in wilc_spi_write()
1100 wilc_spi_reset_cmd_sequence(wilc, i, addr); in wilc_spi_write()
1116 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_reset()
1117 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_reset()
1121 if (result && !spi_priv->probing_crc) in wilc_spi_reset()
1122 dev_err(&spi->dev, "Failed cmd reset\n"); in wilc_spi_reset()
1129 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_is_init()
1131 return spi_priv->isinit; in wilc_spi_is_init()
1136 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_deinit()
1138 spi_priv->isinit = false; in wilc_spi_deinit()
1145 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_init()
1148 if (spi_priv->isinit) { in wilc_spi_init()
1162 spi_priv->isinit = true; in wilc_spi_init()
1169 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_configure_bus_protocol()
1170 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_configure_bus_protocol()
1179 spi_priv->probing_crc = true; in wilc_spi_configure_bus_protocol()
1180 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_configure_bus_protocol()
1181 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ in wilc_spi_configure_bus_protocol()
1186 spi_priv->crc7_enabled = !enable_crc7; in wilc_spi_configure_bus_protocol()
1189 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); in wilc_spi_configure_bus_protocol()
1205 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); in wilc_spi_configure_bus_protocol()
1210 dev_err(&spi->dev, in wilc_spi_configure_bus_protocol()
1216 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_configure_bus_protocol()
1217 spi_priv->crc16_enabled = enable_crc16; in wilc_spi_configure_bus_protocol()
1219 /* re-read to make sure new settings are in effect: */ in wilc_spi_configure_bus_protocol()
1222 spi_priv->probing_crc = false; in wilc_spi_configure_bus_protocol()
1229 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_validate_chipid()
1238 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_validate_chipid()
1242 dev_err(&spi->dev, "Unknown chip id 0x%x\n", chipid); in wilc_validate_chipid()
1243 return -ENODEV; in wilc_validate_chipid()
1253 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); in wilc_spi_read_size()
1261 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, in wilc_spi_read_int()
1273 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1279 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1284 retry--; in wilc_spi_clear_int_ext()
1291 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_sync_ext()
1296 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); in wilc_spi_sync_ext()
1297 return -EINVAL; in wilc_spi_sync_ext()
1305 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1312 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1322 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1327 for (i = 0; (i < 5) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1332 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1339 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1344 for (i = 0; (i < 3) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1349 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()