Lines Matching full:23
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
49 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
117 #define MT_RXV6_NF2 GENMASK(23, 16)
135 #define MT_TXD0_IP_SUM BIT(23)
140 #define MT_TXD1_PROTECTED BIT(23)
153 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
220 #define MT_TXS1_F1_NOISE_2 GENMASK(23, 16)
225 #define MT_TXS2_F1_RCPI_2 GENMASK(23, 16)
230 #define MT_TXS3_RXV_SEQNO GENMASK(23, 16)
235 #define MT_TXS4_AMPDU BIT(23)