Lines Matching full:ml
24 * (ML) = only defined for Monalisa
133 #define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */
134 #define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */
135 #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */
136 #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */
138 #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */
139 #define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */
140 #define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */
142 #define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */
143 #define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */
144 #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */
145 #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */
172 #define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */
173 #define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */
207 #define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */
208 #define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */
223 #define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */
224 #define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */
231 /* External registers (ML) */
251 #define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */
252 #define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */
261 #define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */
262 #define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/
298 #define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
299 #define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
300 #define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
340 #define ALL_IRSR_ML 0x0ffff077L /* (ML) */
350 #define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
351 #define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
352 #define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
438 /* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */
439 /* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */
440 /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */
441 /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */
453 /* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */
454 /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */
455 /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */
463 /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */
470 /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */
479 /* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */
505 /* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */
573 #define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */
574 #define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */
575 #define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */
576 #define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/
578 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/
580 #define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */
619 #define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */
637 #define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */
638 #define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */
655 #define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */
656 #define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */