Lines Matching full:27
94 #define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)
118 #define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27)
184 #define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27)
222 #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
354 #define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY BIT(27)
437 #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
725 #define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)
766 #define MTK_WED_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16)
776 #define MTK_WED_AMSDU_QMEM_FQ_CNT GENMASK(27, 16)
778 #define MTK_WED_AMSDU_QMEM_TID0_QCNT GENMASK(27, 16)
780 #define MTK_WED_AMSDU_QMEM_TID2_QCNT GENMASK(27, 16)
782 #define MTK_WED_AMSDU_QMEM_TID4_QCNT GENMASK(27, 16)
784 #define MTK_WED_AMSDU_QMEM_TID6_QCNT GENMASK(27, 16)
788 #define MTK_WED_AMSDU_QMEM_FQ_HEAD GENMASK(27, 16)
790 #define MTK_WED_AMSDU_QMEM_TID0_QHEAD GENMASK(27, 16)
792 #define MTK_WED_AMSDU_QMEM_TID2_QHEAD GENMASK(27, 16)
794 #define MTK_WED_AMSDU_QMEM_TID4_QHEAD GENMASK(27, 16)
796 #define MTK_WED_AMSDU_QMEM_TID6_QHEAD GENMASK(27, 16)
798 #define MTK_WED_AMSDU_QMEM_FQ_TAIL GENMASK(27, 16)
800 #define MTK_WED_AMSDU_QMEM_TID0_QTAIL GENMASK(27, 16)
802 #define MTK_WED_AMSDU_QMEM_TID2_QTAIL GENMASK(27, 16)
804 #define MTK_WED_AMSDU_QMEM_TID4_QTAIL GENMASK(27, 16)
806 #define MTK_WED_AMSDU_QMEM_TID6_QTAIL GENMASK(27, 16)