Lines Matching +full:0 +full:x20
12 #define USE_FSR BIT(0)
14 #define SPINOR_OP_MT_DIE_ERASE 0xc4 /* Chip (die) erase opcode */
15 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
16 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
17 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
18 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
19 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
20 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
21 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
22 #define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */
23 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
24 #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
27 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
34 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \
35 SPI_MEM_OP_ADDR(naddr, addr, 0), \
37 SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
40 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), \
43 SPI_MEM_OP_DATA_IN(1, buf, 0))
46 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), \
67 buf[0] = SPINOR_MT_OCT_DTR; in micron_st_nor_octal_dtr_en()
76 ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); in micron_st_nor_octal_dtr_en()
85 return 0; in micron_st_nor_octal_dtr_en()
102 buf[0] = SPINOR_MT_EXSPI; in micron_st_nor_octal_dtr_dis()
112 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); in micron_st_nor_octal_dtr_dis()
121 return 0; in micron_st_nor_octal_dtr_dis()
140 0, 20, SPINOR_OP_MT_DTR_RD, in mt35xu512aba_post_sfdp_fixup()
145 nor->params->rdsr_addr_nbytes = 0; in mt35xu512aba_post_sfdp_fixup()
154 return 0; in mt35xu512aba_post_sfdp_fixup()
164 .id = SNOR_ID(0x2c, 0x5b, 0x1a),
174 .id = SNOR_ID(0x2c, 0x5b, 0x1c),
189 return 0; in mt25qu512a_post_bfpt_fixup()
272 .id = SNOR_ID(0x20, 0x20, 0x10),
277 .id = SNOR_ID(0x20, 0x20, 0x11),
282 .id = SNOR_ID(0x20, 0x20, 0x12),
286 .id = SNOR_ID(0x20, 0x20, 0x13),
290 .id = SNOR_ID(0x20, 0x20, 0x14),
294 .id = SNOR_ID(0x20, 0x20, 0x15),
298 .id = SNOR_ID(0x20, 0x20, 0x16),
302 .id = SNOR_ID(0x20, 0x20, 0x17),
306 .id = SNOR_ID(0x20, 0x20, 0x18),
311 .id = SNOR_ID(0x20, 0x40, 0x11),
315 .id = SNOR_ID(0x20, 0x40, 0x14),
319 .id = SNOR_ID(0x20, 0x40, 0x15),
323 .id = SNOR_ID(0x20, 0x63, 0x16),
328 .id = SNOR_ID(0x20, 0x71, 0x14),
332 .id = SNOR_ID(0x20, 0x71, 0x15),
337 .id = SNOR_ID(0x20, 0x71, 0x16),
342 .id = SNOR_ID(0x20, 0x71, 0x17),
346 .id = SNOR_ID(0x20, 0x73, 0x16),
351 .id = SNOR_ID(0x20, 0x80, 0x12),
355 .id = SNOR_ID(0x20, 0x80, 0x14),
359 .id = SNOR_ID(0x20, 0x80, 0x15),
364 .id = SNOR_ID(0x20, 0xba, 0x16),
369 .id = SNOR_ID(0x20, 0xba, 0x17),
374 .id = SNOR_ID(0x20, 0xba, 0x18),
382 .id = SNOR_ID(0x20, 0xba, 0x19, 0x10, 0x44, 0x00),
389 .id = SNOR_ID(0x20, 0xba, 0x19),
395 .id = SNOR_ID(0x20, 0xba, 0x20, 0x10, 0x44, 0x00),
402 .id = SNOR_ID(0x20, 0xba, 0x20),
410 .id = SNOR_ID(0x20, 0xba, 0x21),
419 .id = SNOR_ID(0x20, 0xba, 0x22),
426 .id = SNOR_ID(0x20, 0xbb, 0x15),
431 .id = SNOR_ID(0x20, 0xbb, 0x16),
436 .id = SNOR_ID(0x20, 0xbb, 0x17),
443 .id = SNOR_ID(0x20, 0xbb, 0x18),
451 .id = SNOR_ID(0x20, 0xbb, 0x19, 0x10, 0x44, 0x00),
460 .id = SNOR_ID(0x20, 0xbb, 0x19),
466 .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00),
473 .id = SNOR_ID(0x20, 0xbb, 0x20),
481 .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
486 .id = SNOR_ID(0x20, 0xbb, 0x21),
493 .id = SNOR_ID(0x20, 0xbb, 0x22),
509 * Return: 0 on success, -errno otherwise.
558 NULL, 0); in micron_st_nor_clear_fsr()
571 * Return: 1 if ready, 0 if not ready, -errno on errors.
578 if (sr_ready < 0) in micron_st_nor_ready()
593 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { in micron_st_nor_ready()
594 if (nor->bouncebuf[0] & FSR_E_ERR) in micron_st_nor_ready()
599 if (nor->bouncebuf[0] & FSR_PT_ERR) in micron_st_nor_ready()
618 return sr_ready && !!(nor->bouncebuf[0] & FSR_READY); in micron_st_nor_ready()
638 return 0; in micron_st_nor_late_init()