Lines Matching full:sec

25 /* SeC FW Status Register
39 #define IPC_BASE_ADDR	0x80400 /* SeC IPC Base Address */
46  * the most recent command has been completed by the SEC
79 /* SeC Address Translation Table Entry 2 - Ctrl
81  * This register resides also in SeC's PCI-E Memory space.
100  * interrupts from SeC to host, aggregating both interrupts that
112  * This is the top hierarchy for masking interrupts from SeC to host.
121 /* Host Interrupt Cause Register 0 - SeC IPC Readiness
124  * and it is also exposed in the SeC memory space.
125  * This register is used by SeC's IPC driver in order
138  * and it is also exposed in the SeC memory space.
139  * The register may be used by SeC to ACK a host request for aliveness.
144 /* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */
151  * from SeC to host via HICRs.
187 /* SEC Memory Space IPC output payload.
189  * This register is part of the output payload which SEC provides to host.
193 /* SeC Interrupt Cause Register - Host Aliveness Request
194  * This register is both an ICR to SeC and it is also exposed
196  * The register is used by host to request SeC aliveness.
202 /* SeC Interrupt Cause Register - Host IPC Readiness
204  * This register is both an ICR to SeC and it is also exposed
206  * This register is used by the host's SeC driver uses in order
207  * to synchronize with SeC about IPC interface state.
219 /* SeC Interrupt Cause Register - SeC IPC Output Status
223  * New commands and payloads should not be written by SeC until this