Lines Matching +full:enum +full:- +full:name
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
8 <!-- where does this belong? -->
9 <domain name="VBIF" width="32">
12 <domain name="MDP5" width="32">
14 <enum name="mdp5_intf_type">
15 <value name="INTF_DISABLED" value="0x0"/>
16 <value name="INTF_DSI" value="0x1"/>
17 <value name="INTF_HDMI" value="0x3"/>
18 <value name="INTF_LCDC" value="0x5"/>
19 <value name="INTF_eDP" value="0x9"/>
20 <value name="INTF_VIRTUAL" value="0x64"/>
21 <!-- non-display interfaces are listed below: -->
22 <value name="INTF_WB" value="0x65"/>
23 </enum>
25 <enum name="mdp5_intfnum">
26 <value name="NO_INTF" value="0"/>
27 <value name="INTF0" value="1"/>
28 <value name="INTF1" value="2"/>
29 <value name="INTF2" value="3"/>
30 <value name="INTF3" value="4"/>
31 </enum>
33 <enum name="mdp5_pipe">
34 <value name="SSPP_NONE" value="0"/>
35 <value name="SSPP_VIG0" value="1"/>
36 <value name="SSPP_VIG1" value="2"/>
37 <value name="SSPP_VIG2" value="3"/>
38 <value name="SSPP_RGB0" value="4"/>
39 <value name="SSPP_RGB1" value="5"/>
40 <value name="SSPP_RGB2" value="6"/>
41 <value name="SSPP_DMA0" value="7"/>
42 <value name="SSPP_DMA1" value="8"/>
43 <value name="SSPP_VIG3" value="9"/>
44 <value name="SSPP_RGB3" value="10"/>
45 <value name="SSPP_CURSOR0" value="11"/>
46 <value name="SSPP_CURSOR1" value="12"/>
47 </enum>
49 <enum name="mdp5_format">
50 <!-- TODO -->
51 <value name="DUMMY" value="0"/>
52 </enum>
54 <enum name="mdp5_ctl_mode">
55 <value name="MODE_NONE" value="0"/>
56 <value name="MODE_WB_0_BLOCK" value="1"/>
57 <value name="MODE_WB_1_BLOCK" value="2"/>
58 <value name="MODE_WB_0_LINE" value="3"/>
59 <value name="MODE_WB_1_LINE" value="4"/>
60 <value name="MODE_WB_2_LINE" value="5"/>
61 </enum>
63 <enum name="mdp5_pack_3d">
64 <value name="PACK_3D_FRAME_INT" value="0"/>
65 <value name="PACK_3D_H_ROW_INT" value="1"/>
66 <value name="PACK_3D_V_ROW_INT" value="2"/>
67 <value name="PACK_3D_COL_INT" value="3"/>
68 </enum>
70 <enum name="mdp5_scale_filter">
71 <value name="SCALE_FILTER_NEAREST" value="0"/>
72 <value name="SCALE_FILTER_BIL" value="1"/>
73 <value name="SCALE_FILTER_PCMN" value="2"/>
74 <value name="SCALE_FILTER_CA" value="3"/>
75 </enum>
77 <enum name="mdp5_pipe_bwc">
78 <value name="BWC_LOSSLESS" value="0"/>
79 <value name="BWC_Q_HIGH" value="1"/>
80 <value name="BWC_Q_MED" value="2"/>
81 </enum>
83 <enum name="mdp5_cursor_format">
84 <value name="CURSOR_FMT_ARGB8888" value="0"/>
85 <value name="CURSOR_FMT_ARGB1555" value="2"/>
86 <value name="CURSOR_FMT_ARGB4444" value="4"/>
87 </enum>
89 <enum name="mdp5_cursor_alpha">
90 <value name="CURSOR_ALPHA_CONST" value="0"/>
91 <value name="CURSOR_ALPHA_PER_PIXEL" value="2"/>
92 </enum>
94 <bitset name="MDP5_IRQ">
95 <bitfield name="WB_0_DONE" pos="0" type="boolean"/>
96 <bitfield name="WB_1_DONE" pos="1" type="boolean"/>
97 <bitfield name="WB_2_DONE" pos="4" type="boolean"/>
98 <bitfield name="PING_PONG_0_DONE" pos="8" type="boolean"/>
99 <bitfield name="PING_PONG_1_DONE" pos="9" type="boolean"/>
100 <bitfield name="PING_PONG_2_DONE" pos="10" type="boolean"/>
101 <bitfield name="PING_PONG_3_DONE" pos="11" type="boolean"/>
102 <bitfield name="PING_PONG_0_RD_PTR" pos="12" type="boolean"/>
103 <bitfield name="PING_PONG_1_RD_PTR" pos="13" type="boolean"/>
104 <bitfield name="PING_PONG_2_RD_PTR" pos="14" type="boolean"/>
105 <bitfield name="PING_PONG_3_RD_PTR" pos="15" type="boolean"/>
106 <bitfield name="PING_PONG_0_WR_PTR" pos="16" type="boolean"/>
107 <bitfield name="PING_PONG_1_WR_PTR" pos="17" type="boolean"/>
108 <bitfield name="PING_PONG_2_WR_PTR" pos="18" type="boolean"/>
109 <bitfield name="PING_PONG_3_WR_PTR" pos="19" type="boolean"/>
110 <bitfield name="PING_PONG_0_AUTO_REF" pos="20" type="boolean"/>
111 <bitfield name="PING_PONG_1_AUTO_REF" pos="21" type="boolean"/>
112 <bitfield name="PING_PONG_2_AUTO_REF" pos="22" type="boolean"/>
113 <bitfield name="PING_PONG_3_AUTO_REF" pos="23" type="boolean"/>
114 <bitfield name="INTF0_UNDER_RUN" pos="24" type="boolean"/>
115 <bitfield name="INTF0_VSYNC" pos="25" type="boolean"/>
116 <bitfield name="INTF1_UNDER_RUN" pos="26" type="boolean"/>
117 <bitfield name="INTF1_VSYNC" pos="27" type="boolean"/>
118 <bitfield name="INTF2_UNDER_RUN" pos="28" type="boolean"/>
119 <bitfield name="INTF2_VSYNC" pos="29" type="boolean"/>
120 <bitfield name="INTF3_UNDER_RUN" pos="30" type="boolean"/>
121 <bitfield name="INTF3_VSYNC" pos="31" type="boolean"/>
124 <bitset name="mdp5_smp_alloc" inline="yes">
125 <!-- Use "mdp5_cfg->mdp.smp.clients[enum mdp5_pipe]" instead -->
126 <bitfield name="CLIENT0" low="0" high="7" type="uint"/>
127 <bitfield name="CLIENT1" low="8" high="15" type="uint"/>
128 <bitfield name="CLIENT2" low="16" high="23" type="uint"/>
131 <reg32 offset="0x00000" name="HW_VERSION">
132 <bitfield name="STEP" low="0" high="15" type="uint"/>
133 <bitfield name="MINOR" low="16" high="27" type="uint"/>
134 <bitfield name="MAJOR" low="28" high="31" type="uint"/>
137 <reg32 offset="0x00004" name="DISP_INTF_SEL">
138 <bitfield name="INTF0" low="0" high="7" type="mdp5_intf_type"/>
139 <bitfield name="INTF1" low="8" high="15" type="mdp5_intf_type"/>
140 <bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
141 <bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
143 <reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
144 <reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
145 <reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
146 <reg32 offset="0x0001C" name="HIST_INTR_EN"/>
147 <reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
148 <reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
149 <reg32 offset="0x00028" name="SPARE_0">
150 <bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
153 <array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
154 <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
156 <array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
157 <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
160 <enum name="mdp5_igc_type">
161 <value name="IGC_VIG" value="0"/> <!-- 0x200 -->
162 <value name="IGC_RGB" value="1"/> <!-- 0x210 -->
163 <value name="IGC_DMA" value="2"/> <!-- 0x220 -->
164 <value name="IGC_DSPP" value="3"/> <!-- 0x300 -->
165 </enum>
166 …<array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_i…
167 <array offset="0x00" name="LUT" length="3" stride="4">
168 <reg32 offset="0" name="REG">
169 <bitfield name="VAL" low="0" high="11"/>
170 <bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
171 <!--
175 MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
176 -->
177 <bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
178 <bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
179 <bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
183 <reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
184 <reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
185 <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
186 <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
187 <bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
188 <bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
190 <reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
191 <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
192 <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
193 <bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
194 <bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
197 <!-- check length/index.. -->
198 …rray doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.bas…
199 <array offsets="0x000,0x004,0x008,0x00C,0x010,0x024" name="LAYER" length="6" stride="4">
200 <!--
204 -->
205 <reg32 offset="0" name="REG">
206 <bitfield name="VIG0" low="0" high="2" type="uint"/>
207 <bitfield name="VIG1" low="3" high="5" type="uint"/>
208 <bitfield name="VIG2" low="6" high="8" type="uint"/>
209 <bitfield name="RGB0" low="9" high="11" type="uint"/>
210 <bitfield name="RGB1" low="12" high="14" type="uint"/>
211 <bitfield name="RGB2" low="15" high="17" type="uint"/>
212 <bitfield name="DMA0" low="18" high="20" type="uint"/>
213 <bitfield name="DMA1" low="21" high="23" type="uint"/>
214 <bitfield name="BORDER_COLOR" pos="24" type="boolean"/>
215 <bitfield name="CURSOR_OUT" pos="25" type="boolean"/>
216 <bitfield name="VIG3" low="26" high="28" type="uint"/>
217 <bitfield name="RGB3" low="29" high="31" type="uint"/>
220 <reg32 offset="0x014" name="OP">
221 <bitfield name="MODE" low="0" high="3" type="mdp5_ctl_mode"/>
222 <bitfield name="INTF_NUM" low="4" high="6" type="mdp5_intfnum"/>
223 <bitfield name="CMD_MODE" pos="17" type="boolean"/>
224 <bitfield name="PACK_3D_ENABLE" pos="19" type="boolean"/>
225 <bitfield name="PACK_3D" low="20" high="21" type="mdp5_pack_3d"/>
227 <reg32 offset="0x018" name="FLUSH">
228 <bitfield name="VIG0" pos="0" type="boolean"/>
229 <bitfield name="VIG1" pos="1" type="boolean"/>
230 <bitfield name="VIG2" pos="2" type="boolean"/>
231 <bitfield name="RGB0" pos="3" type="boolean"/>
232 <bitfield name="RGB1" pos="4" type="boolean"/>
233 <bitfield name="RGB2" pos="5" type="boolean"/>
234 <bitfield name="LM0" pos="6" type="boolean"/>
235 <bitfield name="LM1" pos="7" type="boolean"/>
236 <bitfield name="LM2" pos="8" type="boolean"/>
237 <bitfield name="LM3" pos="9" type="boolean"/>
238 <bitfield name="LM4" pos="10" type="boolean"/>
239 <bitfield name="DMA0" pos="11" type="boolean"/>
240 <bitfield name="DMA1" pos="12" type="boolean"/>
241 <bitfield name="DSPP0" pos="13" type="boolean"/>
242 <bitfield name="DSPP1" pos="14" type="boolean"/>
243 <bitfield name="DSPP2" pos="15" type="boolean"/>
244 <bitfield name="WB" pos="16" type="boolean"/>
245 <bitfield name="CTL" pos="17" type="boolean"/>
246 <bitfield name="VIG3" pos="18" type="boolean"/>
247 <bitfield name="RGB3" pos="19" type="boolean"/>
248 <bitfield name="LM5" pos="20" type="boolean"/>
249 <bitfield name="DSPP3" pos="21" type="boolean"/>
250 <bitfield name="CURSOR_0" pos="22" type="boolean"/>
251 <bitfield name="CURSOR_1" pos="23" type="boolean"/>
252 <bitfield name="CHROMADOWN_0" pos="26" type="boolean"/>
253 <bitfield name="TIMING_3" pos="28" type="boolean"/>
254 <bitfield name="TIMING_2" pos="29" type="boolean"/>
255 <bitfield name="TIMING_1" pos="30" type="boolean"/>
256 <bitfield name="TIMING_0" pos="31" type="boolean"/>
258 <reg32 offset="0x01C" name="START"/>
259 <reg32 offset="0x020" name="PACK_3D"/>
260 <array offsets="0x040,0x044,0x048,0x04C,0x050,0x054" name="LAYER_EXT" length="6" stride="4">
261 <reg32 offset="0" name="REG">
262 <bitfield name="VIG0_BIT3" pos="0" type="boolean"/>
263 <bitfield name="VIG1_BIT3" pos="2" type="boolean"/>
264 <bitfield name="VIG2_BIT3" pos="4" type="boolean"/>
265 <bitfield name="VIG3_BIT3" pos="6" type="boolean"/>
266 <bitfield name="RGB0_BIT3" pos="8" type="boolean"/>
267 <bitfield name="RGB1_BIT3" pos="10" type="boolean"/>
268 <bitfield name="RGB2_BIT3" pos="12" type="boolean"/>
269 <bitfield name="RGB3_BIT3" pos="14" type="boolean"/>
270 <bitfield name="DMA0_BIT3" pos="16" type="boolean"/>
271 <bitfield name="DMA1_BIT3" pos="18" type="boolean"/>
272 <bitfield name="CURSOR0" low="20" high="23" type="mdp_mixer_stage_id"/>
273 <bitfield name="CURSOR1" low="26" high="29" type="mdp_mixer_stage_id"/>
278 <enum name="mdp5_data_format">
279 <value name="DATA_FORMAT_RGB" value="0"/>
280 <value name="DATA_FORMAT_YUV" value="1"/>
281 </enum>
283 …->pipe_vig.base[0],mdp5_cfg->pipe_vig.base[1],mdp5_cfg->pipe_vig.base[2],mdp5_cfg->pipe_rgb.base[0…
284 <reg32 offset="0x200" name="OP_MODE">
285 <bitfield name="CSC_DST_DATA_FORMAT" pos="19" type="mdp5_data_format"/>
286 <bitfield name="CSC_SRC_DATA_FORMAT" pos="18" type="mdp5_data_format"/>
287 <bitfield name="CSC_1_EN" pos="17" type="boolean"/>
289 <reg32 offset="0x2C4" name="HIST_CTL_BASE"/>
290 <reg32 offset="0x2F0" name="HIST_LUT_BASE"/>
291 <reg32 offset="0x300" name="HIST_LUT_SWAP"/>
292 <reg32 offset="0x320" name="CSC_1_MATRIX_COEFF_0">
293 <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
294 <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
296 <reg32 offset="0x324" name="CSC_1_MATRIX_COEFF_1">
297 <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
298 <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
300 <reg32 offset="0x328" name="CSC_1_MATRIX_COEFF_2">
301 <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
302 <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
304 <reg32 offset="0x32c" name="CSC_1_MATRIX_COEFF_3">
305 <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
306 <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
308 <reg32 offset="0x330" name="CSC_1_MATRIX_COEFF_4">
309 <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
311 <array offset="0x334" name="CSC_1_PRE_CLAMP" length="3" stride="4">
312 <reg32 offset="0" name="REG">
313 <bitfield name="HIGH" low="0" high="7" type="uint"/>
314 <bitfield name="LOW" low="8" high="15" type="uint"/>
317 <array offset="0x340" name="CSC_1_POST_CLAMP" length="3" stride="4">
318 <reg32 offset="0" name="REG">
319 <bitfield name="HIGH" low="0" high="7" type="uint"/>
320 <bitfield name="LOW" low="8" high="15" type="uint"/>
323 <array offset="0x34c" name="CSC_1_PRE_BIAS" length="3" stride="4">
324 <reg32 offset="0" name="REG">
325 <bitfield name="VALUE" low="0" high="8" type="uint"/>
328 <array offset="0x358" name="CSC_1_POST_BIAS" length="3" stride="4">
329 <reg32 offset="0" name="REG">
330 <bitfield name="VALUE" low="0" high="8" type="uint"/>
333 <!-- SSPP: -->
334 <reg32 offset="0x000" name="SRC_SIZE" type="reg_wh"/>
335 <reg32 offset="0x004" name="SRC_IMG_SIZE" type="reg_wh"/>
336 <reg32 offset="0x008" name="SRC_XY" type="reg_xy"/>
337 <reg32 offset="0x00C" name="OUT_SIZE" type="reg_wh"/>
338 <reg32 offset="0x010" name="OUT_XY" type="reg_xy"/>
339 <reg32 offset="0x014" name="SRC0_ADDR"/>
340 <reg32 offset="0x018" name="SRC1_ADDR"/>
341 <reg32 offset="0x01C" name="SRC2_ADDR"/>
342 <reg32 offset="0x020" name="SRC3_ADDR"/>
343 <reg32 offset="0x024" name="SRC_STRIDE_A">
344 <bitfield name="P0" low="0" high="15" type="uint"/>
345 <bitfield name="P1" low="16" high="31" type="uint"/>
347 <reg32 offset="0x028" name="SRC_STRIDE_B">
348 <bitfield name="P2" low="0" high="15" type="uint"/>
349 <bitfield name="P3" low="16" high="31" type="uint"/>
351 <reg32 offset="0x02C" name="STILE_FRAME_SIZE"/>
352 <reg32 offset="0x030" name="SRC_FORMAT">
353 <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
354 <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
355 <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
356 <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
357 <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
358 <bitfield name="CPP" low="9" high="10" type="uint">
361 <bitfield name="ROT90" pos="11" type="boolean"/>
362 <bitfield name="UNPACK_COUNT" low="12" high="13" type="uint"/>
363 <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
364 <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
365 <bitfield name="FETCH_TYPE" low="19" high="20" type="mdp_fetch_type"/>
366 <bitfield name="CHROMA_SAMP" low="23" high="24" type="mdp_chroma_samp_type"/>
368 <reg32 offset="0x034" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
369 <reg32 offset="0x038" name="SRC_OP_MODE">
370 <bitfield name="BWC_EN" pos="0" type="boolean"/>
371 <bitfield name="BWC" low="1" high="2" type="mdp5_pipe_bwc"/>
372 <bitfield name="FLIP_LR" pos="13" type="boolean"/>
373 <bitfield name="FLIP_UD" pos="14" type="boolean"/>
374 <bitfield name="IGC_EN" pos="16" type="boolean"/>
375 <bitfield name="IGC_ROM_0" pos="17" type="boolean"/>
376 <bitfield name="IGC_ROM_1" pos="18" type="boolean"/>
377 <bitfield name="DEINTERLACE" pos="22" type="boolean"/>
378 <bitfield name="DEINTERLACE_ODD" pos="23" type="boolean"/>
379 <bitfield name="SW_PIX_EXT_OVERRIDE" pos="31" type="boolean"/>
381 <reg32 offset="0x03c" name="SRC_CONSTANT_COLOR"/>
382 <reg32 offset="0x048" name="FETCH_CONFIG"/>
383 <reg32 offset="0x04c" name="VC1_RANGE"/>
384 <reg32 offset="0x050" name="REQPRIO_FIFO_WM_0"/>
385 <reg32 offset="0x054" name="REQPRIO_FIFO_WM_1"/>
386 <reg32 offset="0x058" name="REQPRIO_FIFO_WM_2"/>
387 <reg32 offset="0x070" name="SRC_ADDR_SW_STATUS"/>
388 <reg32 offset="0x0a4" name="CURRENT_SRC0_ADDR"/>
389 <reg32 offset="0x0a8" name="CURRENT_SRC1_ADDR"/>
390 <reg32 offset="0x0ac" name="CURRENT_SRC2_ADDR"/>
391 <reg32 offset="0x0b0" name="CURRENT_SRC3_ADDR"/>
392 <reg32 offset="0x0b4" name="DECIMATION">
393 <bitfield name="VERT" low="0" high="7" type="uint"/>
394 <bitfield name="HORZ" low="8" high="15" type="uint"/>
396 …<array offsets="0x100,0x110,0x120" name="SW_PIX_EXT" length="3" stride="0x10" index="mdp_component…
397 <!--
400 o For signed values (int): + indicates overfetch, - indicates line drop
401 -->
402 <reg32 offset="0x00" name="LR">
403 <bitfield name="LEFT_RPT" low="0" high="7" type="uint"/>
404 <bitfield name="LEFT_OVF" low="8" high="15" type="int"/>
405 <bitfield name="RIGHT_RPT" low="16" high="23" type="uint"/>
406 <bitfield name="RIGHT_OVF" low="24" high="31" type="int"/>
408 <reg32 offset="0x04" name="TB">
409 <bitfield name="TOP_RPT" low="0" high="7" type="uint"/>
410 <bitfield name="TOP_OVF" low="8" high="15" type="int"/>
411 <bitfield name="BOTTOM_RPT" low="16" high="23" type="uint"/>
412 <bitfield name="BOTTOM_OVF" low="24" high="31" type="int"/>
414 <reg32 offset="0x08" name="REQ_PIXELS">
415 <bitfield name="LEFT_RIGHT" low="0" high="15" type="uint"/>
416 <bitfield name="TOP_BOTTOM" low="16" high="31" type="uint"/>
419 <reg32 offset="0x204" name="SCALE_CONFIG">
420 <bitfield name="SCALEX_EN" pos="0" type="boolean"/>
421 <bitfield name="SCALEY_EN" pos="1" type="boolean"/>
422 <bitfield name="SCALEX_FILTER_COMP_0" low="8" high="9" type="mdp5_scale_filter"/>
423 <bitfield name="SCALEY_FILTER_COMP_0" low="10" high="11" type="mdp5_scale_filter"/>
424 <bitfield name="SCALEX_FILTER_COMP_1_2" low="12" high="13" type="mdp5_scale_filter"/>
425 <bitfield name="SCALEY_FILTER_COMP_1_2" low="14" high="15" type="mdp5_scale_filter"/>
426 <bitfield name="SCALEX_FILTER_COMP_3" low="16" high="17" type="mdp5_scale_filter"/>
427 <bitfield name="SCALEY_FILTER_COMP_3" low="18" high="19" type="mdp5_scale_filter"/>
429 <reg32 offset="0x210" name="SCALE_PHASE_STEP_X"/>
430 <reg32 offset="0x214" name="SCALE_PHASE_STEP_Y"/>
431 <reg32 offset="0x218" name="SCALE_CR_PHASE_STEP_X"/>
432 <reg32 offset="0x21c" name="SCALE_CR_PHASE_STEP_Y"/>
433 <reg32 offset="0x220" name="SCALE_INIT_PHASE_X"/>
434 <reg32 offset="0x224" name="SCALE_INIT_PHASE_Y"/>
437 …fsets="mdp5_cfg->lm.base[0],mdp5_cfg->lm.base[1],mdp5_cfg->lm.base[2],mdp5_cfg->lm.base[3],mdp5_cf…
438 <reg32 offset="0x000" name="BLEND_COLOR_OUT">
439 <bitfield name="STAGE0_FG_ALPHA" pos="1" type="boolean"/>
440 <bitfield name="STAGE1_FG_ALPHA" pos="2" type="boolean"/>
441 <bitfield name="STAGE2_FG_ALPHA" pos="3" type="boolean"/>
442 <bitfield name="STAGE3_FG_ALPHA" pos="4" type="boolean"/>
443 <bitfield name="STAGE4_FG_ALPHA" pos="5" type="boolean"/>
444 <bitfield name="STAGE5_FG_ALPHA" pos="6" type="boolean"/>
445 <bitfield name="STAGE6_FG_ALPHA" pos="7" type="boolean"/>
446 <bitfield name="SPLIT_LEFT_RIGHT" pos="31" type="boolean"/>
448 <reg32 offset="0x004" name="OUT_SIZE" type="reg_wh"/>
449 <reg32 offset="0x008" name="BORDER_COLOR_0"/>
450 <reg32 offset="0x010" name="BORDER_COLOR_1"/>
451 <array offsets="0x020,0x050,0x080,0x0B0,0x230,0x260,0x290" name="BLEND" length="7" stride="0x30">
452 <reg32 offset="0x00" name="OP_MODE">
453 <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
454 <bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
455 <bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
456 <bitfield name="FG_INV_MOD_ALPHA" pos="4" type="boolean"/>
457 <bitfield name="FG_TRANSP_EN" pos="5" type="boolean"/>
458 <bitfield name="BG_ALPHA" low="8" high="9" type="mdp_alpha_type"/>
459 <bitfield name="BG_INV_ALPHA" pos="10" type="boolean"/>
460 <bitfield name="BG_MOD_ALPHA" pos="11" type="boolean"/>
461 <bitfield name="BG_INV_MOD_ALPHA" pos="12" type="boolean"/>
462 <bitfield name="BG_TRANSP_EN" pos="13" type="boolean"/>
464 <reg32 offset="0x04" name="FG_ALPHA"/>
465 <reg32 offset="0x08" name="BG_ALPHA"/>
466 <reg32 offset="0x0c" name="FG_TRANSP_LOW0"/>
467 <reg32 offset="0x10" name="FG_TRANSP_LOW1"/>
468 <reg32 offset="0x14" name="FG_TRANSP_HIGH0"/>
469 <reg32 offset="0x18" name="FG_TRANSP_HIGH1"/>
470 <reg32 offset="0x1c" name="BG_TRANSP_LOW0"/>
471 <reg32 offset="0x20" name="BG_TRANSP_LOW1"/>
472 <reg32 offset="0x24" name="BG_TRANSP_HIGH0"/>
473 <reg32 offset="0x28" name="BG_TRANSP_HIGH1"/>
475 <reg32 offset="0x0e0" name="CURSOR_IMG_SIZE">
476 <bitfield name="SRC_W" low="0" high="15" type="uint"/>
477 <bitfield name="SRC_H" low="16" high="31" type="uint"/>
479 <reg32 offset="0x0e4" name="CURSOR_SIZE">
480 <bitfield name="ROI_W" low="0" high="15" type="uint"/>
481 <bitfield name="ROI_H" low="16" high="31" type="uint"/>
483 <reg32 offset="0x0e8" name="CURSOR_XY">
484 <bitfield name="SRC_X" low="0" high="15" type="uint"/>
485 <bitfield name="SRC_Y" low="16" high="31" type="uint"/>
487 <reg32 offset="0x0dc" name="CURSOR_STRIDE">
488 <bitfield name="STRIDE" low="0" high="15" type="uint"/>
490 <reg32 offset="0x0ec" name="CURSOR_FORMAT">
491 <bitfield name="FORMAT" low="0" high="2" type="mdp5_cursor_format"/>
493 <reg32 offset="0x0f0" name="CURSOR_BASE_ADDR"/>
494 <reg32 offset="0x0f4" name="CURSOR_START_XY">
495 <bitfield name="X_START" low="0" high="15" type="uint"/>
496 <bitfield name="Y_START" low="16" high="31" type="uint"/>
498 <reg32 offset="0x0f8" name="CURSOR_BLEND_CONFIG">
499 <bitfield name="BLEND_EN" pos="0" type="boolean"/>
500 <bitfield name="BLEND_ALPHA_SEL" low="1" high="2" type="mdp5_cursor_alpha"/>
501 <bitfield name="BLEND_TRANSP_EN" pos="3" type="boolean"/>
503 <reg32 offset="0x0fc" name="CURSOR_BLEND_PARAM"/>
504 <reg32 offset="0x100" name="CURSOR_BLEND_TRANSP_LOW0"/>
505 <reg32 offset="0x104" name="CURSOR_BLEND_TRANSP_LOW1"/>
506 <reg32 offset="0x108" name="CURSOR_BLEND_TRANSP_HIGH0"/>
507 <reg32 offset="0x10c" name="CURSOR_BLEND_TRANSP_HIGH1"/>
508 <reg32 offset="0x110" name="GC_LUT_BASE"/>
511 …<array doffsets="mdp5_cfg->dspp.base[0],mdp5_cfg->dspp.base[1],mdp5_cfg->dspp.base[2],mdp5_cfg->ds…
512 <reg32 offset="0x000" name="OP_MODE">
513 <bitfield name="IGC_LUT_EN" pos="0" type="boolean"/>
514 <bitfield name="IGC_TBL_IDX" low="1" high="3" type="uint"/>
515 <bitfield name="PCC_EN" pos="4" type="boolean"/>
516 <bitfield name="DITHER_EN" pos="8" type="boolean"/>
517 <bitfield name="HIST_EN" pos="16" type="boolean"/>
518 <bitfield name="AUTO_CLEAR" pos="17" type="boolean"/>
519 <bitfield name="HIST_LUT_EN" pos="19" type="boolean"/>
520 <bitfield name="PA_EN" pos="20" type="boolean"/>
521 <bitfield name="GAMUT_EN" pos="23" type="boolean"/>
522 <bitfield name="GAMUT_ORDER" pos="24" type="boolean"/>
524 <reg32 offset="0x030" name="PCC_BASE"/>
525 <reg32 offset="0x150" name="DITHER_DEPTH"/>
526 <reg32 offset="0x210" name="HIST_CTL_BASE"/>
527 <reg32 offset="0x230" name="HIST_LUT_BASE"/>
528 <reg32 offset="0x234" name="HIST_LUT_SWAP"/>
529 <reg32 offset="0x238" name="PA_BASE"/>
530 <reg32 offset="0x2dc" name="GAMUT_BASE"/>
531 <reg32 offset="0x2b0" name="GC_BASE"/>
534 …<array doffsets="mdp5_cfg->pp.base[0],mdp5_cfg->pp.base[1],mdp5_cfg->pp.base[2],mdp5_cfg->pp.base[…
535 <reg32 offset="0x000" name="TEAR_CHECK_EN"/>
536 <reg32 offset="0x004" name="SYNC_CONFIG_VSYNC">
537 <bitfield name="COUNT" low="0" high="18" type="uint"/>
538 <bitfield name="COUNTER_EN" pos="19" type="boolean"/>
539 <bitfield name="IN_EN" pos="20" type="boolean"/>
541 <reg32 offset="0x008" name="SYNC_CONFIG_HEIGHT"/>
542 <reg32 offset="0x00c" name="SYNC_WRCOUNT">
543 <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
544 <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
546 <reg32 offset="0x010" name="VSYNC_INIT_VAL"/>
547 <reg32 offset="0x014" name="INT_COUNT_VAL">
548 <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
549 <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
551 <reg32 offset="0x018" name="SYNC_THRESH">
552 <bitfield name="START" low="0" high="15" type="uint"/>
553 <bitfield name="CONTINUE" low="16" high="31" type="uint"/>
555 <reg32 offset="0x01c" name="START_POS"/>
556 <reg32 offset="0x020" name="RD_PTR_IRQ"/>
557 <reg32 offset="0x024" name="WR_PTR_IRQ"/>
558 <reg32 offset="0x028" name="OUT_LINE_COUNT"/>
559 <reg32 offset="0x02c" name="PP_LINE_COUNT"/>
560 <reg32 offset="0x030" name="AUTOREFRESH_CONFIG"/>
561 <reg32 offset="0x034" name="FBC_MODE"/>
562 <reg32 offset="0x038" name="FBC_BUDGET_CTL"/>
563 <reg32 offset="0x03c" name="FBC_LOSSY_MODE"/>
566 <enum name="mdp5_block_size">
567 <value name="BLOCK_SIZE_64" value="0"/>
568 <value name="BLOCK_SIZE_128" value="1"/>
569 </enum>
571 <enum name="mdp5_rotate_mode">
572 <value name="ROTATE_0" value="0"/>
573 <value name="ROTATE_90" value="1"/>
574 </enum>
576 <enum name="mdp5_chroma_downsample_method">
577 <value name="DS_MTHD_NO_PIXEL_DROP" value="0"/>
578 <value name="DS_MTHD_PIXEL_DROP" value="1"/>
579 </enum>
581 …<array doffsets="mdp5_cfg->wb.base[0],mdp5_cfg->wb.base[1],mdp5_cfg->wb.base[2],mdp5_cfg->wb.base[…
582 <reg32 offset="0x000" name="DST_FORMAT">
583 <bitfield name="DSTC0_OUT" low="0" high="1" type="uint"/>
584 <bitfield name="DSTC1_OUT" low="2" high="3" type="uint"/>
585 <bitfield name="DSTC2_OUT" low="4" high="5" type="uint"/>
586 <bitfield name="DSTC3_OUT" low="6" high="7" type="uint"/>
587 <bitfield name="DSTC3_EN" pos="8" type="boolean"/>
588 <bitfield name="DST_BPP" low="9" high="10" type="uint"/>
589 <bitfield name="PACK_COUNT" low="12" high="13" type="uint"/>
590 <bitfield name="DST_ALPHA_X" pos="14" type="boolean"/>
591 <bitfield name="PACK_TIGHT" pos="17" type="boolean"/>
592 <bitfield name="PACK_ALIGN_MSB" pos="18" type="boolean"/>
593 <bitfield name="WRITE_PLANES" low="19" high="20" type="uint"/>
594 <bitfield name="DST_DITHER_EN" pos="22" type="boolean"/>
595 <bitfield name="DST_CHROMA_SAMP" low="23" high="25" type="uint"/>
596 <bitfield name="DST_CHROMA_SITE" low="26" high="29" type="uint"/>
597 <bitfield name="FRAME_FORMAT" low="30" high="31" type="uint"/>
599 <reg32 offset="0x004" name="DST_OP_MODE">
600 <bitfield name="BWC_ENC_EN" pos="0" type="boolean"/>
601 <bitfield name="BWC_ENC_OP" low="1" high="2" type="uint"/>
602 <bitfield name="BLOCK_SIZE" low="4" high="4" type="uint"/>
603 <bitfield name="ROT_MODE" low="5" high="5" type="uint"/>
604 <bitfield name="ROT_EN" pos="6" type="boolean"/>
605 <bitfield name="CSC_EN" pos="8" type="boolean"/>
606 <bitfield name="CSC_SRC_DATA_FORMAT" low="9" high="9" type="uint"/>
607 <bitfield name="CSC_DST_DATA_FORMAT" low="10" high="10" type="uint"/>
608 <bitfield name="CHROMA_DWN_SAMPLE_EN" pos="11" type="boolean"/>
609 <bitfield name="CHROMA_DWN_SAMPLE_FORMAT" low="12" high="12" type="uint"/>
610 <bitfield name="CHROMA_DWN_SAMPLE_H_MTHD" low="13" high="13" type="uint"/>
611 <bitfield name="CHROMA_DWN_SAMPLE_V_MTHD" low="14" high="14" type="uint"/>
613 <reg32 offset="0x008" name="DST_PACK_PATTERN">
614 <bitfield name="ELEMENT0" low="0" high="1" type="uint"/>
615 <bitfield name="ELEMENT1" low="8" high="9" type="uint"/>
616 <bitfield name="ELEMENT2" low="16" high="17" type="uint"/>
617 <bitfield name="ELEMENT3" low="24" high="25" type="uint"/>
619 <reg32 offset="0x00c" name="DST0_ADDR"/>
620 <reg32 offset="0x010" name="DST1_ADDR"/>
621 <reg32 offset="0x014" name="DST2_ADDR"/>
622 <reg32 offset="0x018" name="DST3_ADDR"/>
623 <reg32 offset="0x01c" name="DST_YSTRIDE0">
624 <bitfield name="DST0_YSTRIDE" low="0" high="15" type="uint"/>
625 <bitfield name="DST1_YSTRIDE" low="16" high="31" type="uint"/>
627 <reg32 offset="0x020" name="DST_YSTRIDE1">
628 <bitfield name="DST2_YSTRIDE" low="0" high="15" type="uint"/>
629 <bitfield name="DST3_YSTRIDE" low="16" high="31" type="uint"/>
631 <reg32 offset="0x024" name="DST_DITHER_BITDEPTH"/>
632 <reg32 offset="0x030" name="DITHER_MATRIX_ROW0"/>
633 <reg32 offset="0x034" name="DITHER_MATRIX_ROW1"/>
634 <reg32 offset="0x038" name="DITHER_MATRIX_ROW2"/>
635 <reg32 offset="0x03c" name="DITHER_MATRIX_ROW3"/>
636 <reg32 offset="0x048" name="DST_WRITE_CONFIG"/>
637 <reg32 offset="0x050" name="ROTATION_DNSCALER"/>
638 <reg32 offset="0x060" name="N16_INIT_PHASE_X_0_3"/>
639 <reg32 offset="0x064" name="N16_INIT_PHASE_X_1_2"/>
640 <reg32 offset="0x068" name="N16_INIT_PHASE_Y_0_3"/>
641 <reg32 offset="0x06c" name="N16_INIT_PHASE_Y_1_2"/>
642 <reg32 offset="0x074" name="OUT_SIZE">
643 <bitfield name="DST_W" low="0" high="15" type="uint"/>
644 <bitfield name="DST_H" low="16" high="31" type="uint"/>
646 <reg32 offset="0x078" name="ALPHA_X_VALUE"/>
647 <reg32 offset="0x260" name="CSC_MATRIX_COEFF_0">
648 <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
649 <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
651 <reg32 offset="0x264" name="CSC_MATRIX_COEFF_1">
652 <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
653 <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
655 <reg32 offset="0x268" name="CSC_MATRIX_COEFF_2">
656 <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
657 <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
659 <reg32 offset="0x26c" name="CSC_MATRIX_COEFF_3">
660 <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
661 <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
663 <reg32 offset="0x270" name="CSC_MATRIX_COEFF_4">
664 <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
666 <array offset="0x274" name="CSC_COMP_PRECLAMP" length="3" stride="4">
667 <reg32 offset="0" name="REG">
668 <bitfield name="HIGH" low="0" high="7" type="uint"/>
669 <bitfield name="LOW" low="8" high="15" type="uint"/>
672 <array offset="0x280" name="CSC_COMP_POSTCLAMP" length="3" stride="4">
673 <reg32 offset="0" name="REG">
674 <bitfield name="HIGH" low="0" high="7" type="uint"/>
675 <bitfield name="LOW" low="8" high="15" type="uint"/>
678 <array offset="0x28c" name="CSC_COMP_PREBIAS" length="3" stride="4">
679 <reg32 offset="0" name="REG">
680 <bitfield name="VALUE" low="0" high="8" type="uint"/>
683 <array offset="0x298" name="CSC_COMP_POSTBIAS" length="3" stride="4">
684 <reg32 offset="0" name="REG">
685 <bitfield name="VALUE" low="0" high="8" type="uint"/>
690 …y doffsets="mdp5_cfg->intf.base[0],mdp5_cfg->intf.base[1],mdp5_cfg->intf.base[2],mdp5_cfg->intf.ba…
691 <reg32 offset="0x000" name="TIMING_ENGINE_EN"/>
692 <reg32 offset="0x004" name="CONFIG"/>
693 <reg32 offset="0x008" name="HSYNC_CTL">
694 <bitfield name="PULSEW" low="0" high="15" type="uint"/>
695 <bitfield name="PERIOD" low="16" high="31" type="uint"/>
697 <reg32 offset="0x00c" name="VSYNC_PERIOD_F0" type="uint"/>
698 <reg32 offset="0x010" name="VSYNC_PERIOD_F1" type="uint"/>
699 <reg32 offset="0x014" name="VSYNC_LEN_F0" type="uint"/>
700 <reg32 offset="0x018" name="VSYNC_LEN_F1" type="uint"/>
701 <reg32 offset="0x01c" name="DISPLAY_VSTART_F0" type="uint"/>
702 <reg32 offset="0x020" name="DISPLAY_VSTART_F1" type="uint"/>
703 <reg32 offset="0x024" name="DISPLAY_VEND_F0" type="uint"/>
704 <reg32 offset="0x028" name="DISPLAY_VEND_F1" type="uint"/>
705 <reg32 offset="0x02c" name="ACTIVE_VSTART_F0">
706 <bitfield name="VAL" low="0" high="30" type="uint"/>
707 <bitfield name="ACTIVE_V_ENABLE" pos="31" type="boolean"/>
709 <reg32 offset="0x030" name="ACTIVE_VSTART_F1">
710 <bitfield name="VAL" low="0" high="30" type="uint"/>
712 <reg32 offset="0x034" name="ACTIVE_VEND_F0" type="uint"/>
713 <reg32 offset="0x038" name="ACTIVE_VEND_F1" type="uint"/>
714 <reg32 offset="0x03c" name="DISPLAY_HCTL">
715 <bitfield name="START" low="0" high="15" type="uint"/>
716 <bitfield name="END" low="16" high="31" type="uint"/>
718 <reg32 offset="0x040" name="ACTIVE_HCTL">
719 <bitfield name="START" low="0" high="14" type="uint"/>
720 <bitfield name="END" low="16" high="30" type="uint"/>
721 <bitfield name="ACTIVE_H_ENABLE" pos="31" type="boolean"/>
723 <reg32 offset="0x044" name="BORDER_COLOR"/>
724 <reg32 offset="0x048" name="UNDERFLOW_COLOR"/>
725 <reg32 offset="0x04c" name="HSYNC_SKEW"/>
726 <reg32 offset="0x050" name="POLARITY_CTL">
727 <bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
728 <bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
729 <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
731 <reg32 offset="0x054" name="TEST_CTL"/>
732 <reg32 offset="0x058" name="TP_COLOR0"/>
733 <reg32 offset="0x05c" name="TP_COLOR1"/>
734 <reg32 offset="0x084" name="DSI_CMD_MODE_TRIGGER_EN"/>
735 <reg32 offset="0x090" name="PANEL_FORMAT" type="mdp5_format"/>
736 <reg32 offset="0x0a8" name="FRAME_LINE_COUNT_EN"/>
737 <reg32 offset="0x0ac" name="FRAME_COUNT"/>
738 <reg32 offset="0x0b0" name="LINE_COUNT"/>
739 <reg32 offset="0x0f0" name="DEFLICKER_CONFIG"/>
740 <reg32 offset="0x0f4" name="DEFLICKER_STRNG_COEFF"/>
741 <reg32 offset="0x0f8" name="DEFLICKER_WEAK_COEFF"/>
742 <reg32 offset="0x100" name="TPG_ENABLE"/>
743 <reg32 offset="0x104" name="TPG_MAIN_CONTROL"/>
744 <reg32 offset="0x108" name="TPG_VIDEO_CONFIG"/>
745 <reg32 offset="0x10c" name="TPG_COMPONENT_LIMITS"/>
746 <reg32 offset="0x110" name="TPG_RECTANGLE"/>
747 <reg32 offset="0x114" name="TPG_INITIAL_VALUE"/>
748 <reg32 offset="0x118" name="TPG_BLK_WHITE_PATTERN_FRAME"/>
749 <reg32 offset="0x11c" name="TPG_RGB_MAPPING"/>
752 <array doffsets="mdp5_cfg->ad.base[0],mdp5_cfg->ad.base[1]" name="AD" length="2" stride="0x200">
753 <reg32 offset="0x000" name="BYPASS"/>
754 <reg32 offset="0x004" name="CTRL_0"/>
755 <reg32 offset="0x008" name="CTRL_1"/>
756 <reg32 offset="0x00c" name="FRAME_SIZE"/>
757 <reg32 offset="0x010" name="CON_CTRL_0"/>
758 <reg32 offset="0x014" name="CON_CTRL_1"/>
759 <reg32 offset="0x018" name="STR_MAN"/>
760 <reg32 offset="0x01c" name="VAR"/>
761 <reg32 offset="0x020" name="DITH"/>
762 <reg32 offset="0x024" name="DITH_CTRL"/>
763 <reg32 offset="0x028" name="AMP_LIM"/>
764 <reg32 offset="0x02c" name="SLOPE"/>
765 <reg32 offset="0x030" name="BW_LVL"/>
766 <reg32 offset="0x034" name="LOGO_POS"/>
767 <reg32 offset="0x038" name="LUT_FI"/>
768 <reg32 offset="0x07c" name="LUT_CC"/>
769 <reg32 offset="0x0c8" name="STR_LIM"/>
770 <reg32 offset="0x0cc" name="CALIB_AB"/>
771 <reg32 offset="0x0d0" name="CALIB_CD"/>
772 <reg32 offset="0x0d4" name="MODE_SEL"/>
773 <reg32 offset="0x0d8" name="TFILT_CTRL"/>
774 <reg32 offset="0x0dc" name="BL_MINMAX"/>
775 <reg32 offset="0x0e0" name="BL"/>
776 <reg32 offset="0x0e8" name="BL_MAX"/>
777 <reg32 offset="0x0ec" name="AL"/>
778 <reg32 offset="0x0f0" name="AL_MIN"/>
779 <reg32 offset="0x0f4" name="AL_FILT"/>
780 <reg32 offset="0x0f8" name="CFG_BUF"/>
781 <reg32 offset="0x100" name="LUT_AL"/>
782 <reg32 offset="0x144" name="TARG_STR"/>
783 <reg32 offset="0x148" name="START_CALC"/>
784 <reg32 offset="0x14c" name="STR_OUT"/>
785 <reg32 offset="0x154" name="BL_OUT"/>
786 <reg32 offset="0x158" name="CALC_DONE"/>