Lines Matching +full:0 +full:x1ff
9 #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
10 #define DSPARB_CSTART_MASK (0x7f << 7)
12 #define DSPARB_BSTART_MASK (0x7f)
13 #define DSPARB_BSTART_SHIFT 0
15 #define DSPARB_AEND_SHIFT 0
16 #define DSPARB_SPRITEA_SHIFT_VLV 0
17 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
19 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
21 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
23 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
24 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
25 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
26 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
28 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
30 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
32 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
34 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
36 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
37 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
38 #define DSPARB_SPRITEE_SHIFT_VLV 0
39 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
41 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
44 #define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
46 #define DSPFW_SR_MASK (0x1ff << 23)
48 #define DSPFW_CURSORB_MASK (0x3f << 16)
50 #define DSPFW_PLANEB_MASK (0x7f << 8)
51 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
52 #define DSPFW_PLANEA_SHIFT 0
53 #define DSPFW_PLANEA_MASK (0x7f << 0)
54 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
55 #define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
58 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
60 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
62 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
63 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
65 #define DSPFW_CURSORA_MASK (0x3f << 8)
66 #define DSPFW_PLANEC_OLD_SHIFT 0
67 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
68 #define DSPFW_SPRITEA_SHIFT 0
69 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
70 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
71 #define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
75 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
77 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
78 #define DSPFW_HPLL_SR_SHIFT 0
79 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
82 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
84 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
86 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
87 #define DSPFW_SPRITEA_WM1_SHIFT 0
88 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
89 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
91 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
93 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
95 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
96 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
97 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
98 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
99 #define DSPFW_SR_WM1_SHIFT 0
100 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
101 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
102 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
104 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
106 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
108 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
109 #define DSPFW_SPRITEC_SHIFT 0
110 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
111 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
113 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
115 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
117 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
118 #define DSPFW_SPRITEE_SHIFT 0
119 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
120 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
122 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
124 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
126 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
127 #define DSPFW_CURSORC_SHIFT 0
128 #define DSPFW_CURSORC_MASK (0x3f << 0)
131 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
150 #define DSPFW_PLANEA_HI_SHIFT 0
151 #define DSPFW_PLANEA_HI_MASK (1 << 0)
152 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
171 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
172 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
175 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
178 #define DDL_PLANE_SHIFT 0
180 #define DDL_PRECISION_LOW (0 << 7)
181 #define DRAIN_LATENCY_MASK 0x7f
196 #define VALLEYVIEW_MAX_WM 0xff
197 #define G4X_MAX_WM 0x3f
198 #define I915_MAX_WM 0x3f
202 #define PINEVIEW_MAX_WM 0x1ff
203 #define PINEVIEW_DFT_WM 0x3f
204 #define PINEVIEW_DFT_HPLLOFF_WM 0
207 #define PINEVIEW_CURSOR_MAX_WM 0x3f
208 #define PINEVIEW_CURSOR_DFT_WM 0
217 #define _WM0_PIPEA_ILK 0x45100
218 #define _WM0_PIPEB_ILK 0x45104
219 #define _WM0_PIPEC_IVB 0x45200
220 #define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \
224 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
228 #define WM1_LP_ILK _MMIO(0x45108)
229 #define WM2_LP_ILK _MMIO(0x4510c)
230 #define WM3_LP_ILK _MMIO(0x45110)
236 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
242 #define WM1S_LP_ILK _MMIO(0x45120)
243 #define WM2S_LP_IVB _MMIO(0x45124)
244 #define WM3S_LP_IVB _MMIO(0x45128)
246 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
249 #define WM_MISC _MMIO(0x45260)
250 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
252 #define WM_DBG _MMIO(0x45280)
253 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)